[PATCH]: c263b27a2d target/mips32: fix wrong SRL opcode

[gerrit]

This is an automated email from Gerrit.

"Matsievskiy S.V. <matsievski...@gmail.com>" just uploaded a new patch set to 
Gerrit, which you can find at https://review.openocd.org/c/openocd/+/7968

-- gerrit

commit c263b27a2d32f0bcd0eefe4756f506398cbb5600
Author: Matsievskiy S.V. <matsievski...@gmail.com>
Date:   Wed Nov 8 14:32:57 2023 +0300

    target/mips32: fix wrong SRL opcode
    
    Fix wrong SRL opcode from 0x3 to 0x2 as per [MIPS32 Instruction Set Manual 
MD00086](https://mips.com/products/architectures/mips32-2/)
    
    Change-Id: I126a7b2f87a2d948d9ef0c0cc34b6be6ce6d30dc
    Signed-off-by: Matsievskiy S.V. <matsievski...@gmail.com>

diff --git a/src/target/mips32.h b/src/target/mips32.h
index 3d03e98c58..a67d08b0ae 100644
--- a/src/target/mips32.h
+++ b/src/target/mips32.h
@@ -163,7 +163,7 @@ struct mips32_algorithm {
 #define MIPS32_OP_XORI 0x0Eu
 #define MIPS32_OP_XOR  0x26u
 #define MIPS32_OP_SLTU 0x2Bu
-#define MIPS32_OP_SRL  0x03u
+#define MIPS32_OP_SRL  0x02u
 #define MIPS32_OP_SYNCI        0x1Fu
 #define MIPS32_OP_SLL  0x00u
 #define MIPS32_OP_SLTI 0x0Au

--