This is an automated email from Gerrit.
"Carlos Sanchez <carlossanc...@geotab.com>" just uploaded a new patch set to
Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8008
-- gerrit
commit af42fa6cc910b09c43be05d50ca74b6b04ae1f4a
Author: Sven van Ashbrook <svenvanasbro...@geotab.com>
Date: Fri Apr 29 11:03:13 2022 -0400
flash/nor/kinetis: Eliminate dependency on fcfg2
Prepare for introduction of S32K. Not every kinetis chip has the
same FCFG2 layout. Eliminate kinetis.c's dependency on FCFG2
layout.
Change-Id: I191b80f875d80b774b3304a4c7b1368cbd8b3b7f
Signed-off-by: Sven van Ashbrook <svenvanasbro...@geotab.com>
diff --git a/src/flash/nor/kinetis.c b/src/flash/nor/kinetis.c
index f17f76766f..1fbfccac80 100644
--- a/src/flash/nor/kinetis.c
+++ b/src/flash/nor/kinetis.c
@@ -257,9 +257,8 @@ struct kinetis_chip {
bool probed;
uint32_t sim_fcfg1;
- uint32_t sim_fcfg2;
- uint32_t fcfg2_maxaddr0_shifted;
- uint32_t fcfg2_maxaddr1_shifted;
+ uint32_t maxaddr0_shifted;
+ uint32_t maxaddr1_shifted;
unsigned num_pflash_blocks, num_nvm_blocks;
unsigned pflash_sector_size, nvm_sector_size;
@@ -311,6 +310,7 @@ struct kinetis_chip {
struct kinetis_flash_bank banks[KINETIS_MAX_BANKS];
int (*probe_chip)(struct kinetis_chip *k_chip);
+ int (*bank_verify_maxaddr)(struct flash_bank *bank);
};
struct kinetis_type {
@@ -394,6 +394,7 @@ static int kinetis_write_inner(struct flash_bank *bank,
const uint8_t *buffer,
uint32_t offset, uint32_t count);
static int kinetis_probe_chip(struct kinetis_chip *k_chip);
static int s32k_probe_chip(struct kinetis_chip *k_chip);
+static int kinetis_bank_verify_maxaddr(struct flash_bank *bank);
static int kinetis_auto_probe(struct flash_bank *bank);
@@ -880,8 +881,10 @@ static int kinetis_chip_options(struct kinetis_chip
*k_chip, int argc, const cha
if (i + 1 < argc)
k_chip->sim_base = strtoul(argv[++i], NULL, 0);
} else if (strcmp(argv[i], "-chipname") == 0) {
- if (i + 1 < argc && strcmp(argv[++i], "s32k") == 0)
+ if (i + 1 < argc && strcmp(argv[++i], "s32k") == 0) {
k_chip->probe_chip = s32k_probe_chip;
+ k_chip->bank_verify_maxaddr = NULL;
+ }
} else
LOG_ERROR("Unsupported flash bank option %s", argv[i]);
}
@@ -911,6 +914,7 @@ FLASH_BANK_COMMAND_HANDLER(kinetis_flash_bank_command)
k_chip->target = target;
k_chip->probe_chip = kinetis_probe_chip;
+ k_chip->bank_verify_maxaddr = kinetis_bank_verify_maxaddr;
/* only the first defined bank can define chip options */
retval = kinetis_chip_options(k_chip, CMD_ARGC - 6, CMD_ARGV +
6);
@@ -2070,7 +2074,7 @@ static int kinetis_probe_chip(struct kinetis_chip *k_chip)
uint32_t ee_size = 0;
uint32_t pflash_size_k, nvm_size_k, dflash_size_k;
uint32_t pflash_size_m;
- uint32_t sim_sdid;
+ uint32_t sim_sdid, sim_fcfg2;
unsigned num_blocks = 0;
unsigned maxaddr_shift = 13;
struct target *target = k_chip->target;
@@ -2518,30 +2522,30 @@ static int kinetis_probe_chip(struct kinetis_chip
*k_chip)
if (result != ERROR_OK)
return result;
- result = target_read_u32(target, k_chip->sim_base + SIM_FCFG2_OFFSET,
&k_chip->sim_fcfg2);
+ result = target_read_u32(target, k_chip->sim_base + SIM_FCFG2_OFFSET,
&sim_fcfg2);
if (result != ERROR_OK)
return result;
LOG_DEBUG("SDID: 0x%08" PRIX32 " FCFG1: 0x%08" PRIX32 " FCFG2: 0x%08"
PRIX32, sim_sdid,
- k_chip->sim_fcfg1, k_chip->sim_fcfg2);
+ k_chip->sim_fcfg1, sim_fcfg2);
fcfg1_nvmsize = (uint8_t)((k_chip->sim_fcfg1 >> 28) & 0x0f);
fcfg1_pfsize = (uint8_t)((k_chip->sim_fcfg1 >> 24) & 0x0f);
fcfg1_eesize = (uint8_t)((k_chip->sim_fcfg1 >> 16) & 0x0f);
fcfg1_depart = (uint8_t)((k_chip->sim_fcfg1 >> 8) & 0x0f);
- fcfg2_pflsh = (uint8_t)((k_chip->sim_fcfg2 >> 23) & 0x01);
- k_chip->fcfg2_maxaddr0_shifted = ((k_chip->sim_fcfg2 >> 24) & 0x7f) <<
maxaddr_shift;
- k_chip->fcfg2_maxaddr1_shifted = ((k_chip->sim_fcfg2 >> 16) & 0x7f) <<
maxaddr_shift;
+ fcfg2_pflsh = (uint8_t)((sim_fcfg2 >> 23) & 0x01);
+ k_chip->maxaddr0_shifted = ((sim_fcfg2 >> 24) & 0x7f) << maxaddr_shift;
+ k_chip->maxaddr1_shifted = ((sim_fcfg2 >> 16) & 0x7f) << maxaddr_shift;
if (num_blocks == 0)
- num_blocks = k_chip->fcfg2_maxaddr1_shifted ? 2 : 1;
- else if (k_chip->fcfg2_maxaddr1_shifted == 0 && num_blocks >= 2 &&
fcfg2_pflsh) {
+ num_blocks = k_chip->maxaddr1_shifted ? 2 : 1;
+ else if (k_chip->maxaddr1_shifted == 0 && num_blocks >= 2 &&
fcfg2_pflsh) {
/* fcfg2_maxaddr1 may be zero due to partitioning whole NVM as
EEPROM backup
* Do not adjust block count in this case! */
num_blocks = 1;
LOG_WARNING("MAXADDR1 is zero, number of flash banks adjusted
to 1");
- } else if (k_chip->fcfg2_maxaddr1_shifted != 0 && num_blocks == 1) {
+ } else if (k_chip->maxaddr1_shifted != 0 && num_blocks == 1) {
num_blocks = 2;
LOG_WARNING("MAXADDR1 is non zero, number of flash banks
adjusted to 2");
}
@@ -2637,9 +2641,9 @@ static int kinetis_probe_chip(struct kinetis_chip *k_chip)
* Checking fcfg2_maxaddr0 in bank probe is pointless then
*/
if (fcfg2_pflsh)
- k_chip->pflash_size = k_chip->fcfg2_maxaddr0_shifted *
num_blocks;
+ k_chip->pflash_size = k_chip->maxaddr0_shifted *
num_blocks;
else
- k_chip->pflash_size = k_chip->fcfg2_maxaddr0_shifted *
num_blocks / 2;
+ k_chip->pflash_size = k_chip->maxaddr0_shifted *
num_blocks / 2;
if (k_chip->pflash_size != 2048<<10)
LOG_WARNING("SIM_FCFG1 PFSIZE = 0xf: please check if
pflash is %" PRIu32 " KB", k_chip->pflash_size>>10);
@@ -2693,10 +2697,45 @@ static int kinetis_probe_chip(struct kinetis_chip
*k_chip)
return ERROR_OK;
}
+static int kinetis_bank_verify_maxaddr(struct flash_bank *bank)
+{
+ struct kinetis_flash_bank *k_bank = bank->driver_priv;
+ struct kinetis_chip *k_chip = k_bank->k_chip;
+
+ uint8_t fcfg2_maxaddr0, fcfg2_pflsh, fcfg2_maxaddr1;
+ unsigned int first_nvm_bank = k_chip->num_pflash_blocks;
+ uint32_t sim_fcfg2;
+ int result;
+
+ result = target_read_u32(k_chip->target, k_chip->sim_base +
SIM_FCFG2_OFFSET, &sim_fcfg2);
+ if (result != ERROR_OK)
+ return result;
+
+ fcfg2_pflsh = (uint8_t)((sim_fcfg2 >> 23) & 0x01);
+ fcfg2_maxaddr0 = (uint8_t)((sim_fcfg2 >> 24) & 0x7f);
+ fcfg2_maxaddr1 = (uint8_t)((sim_fcfg2 >> 16) & 0x7f);
+
+ if (k_bank->bank_number == 0 && k_chip->maxaddr0_shifted != bank->size)
+ LOG_WARNING("MAXADDR0 0x%02" PRIx8 " check failed,"
+ " please report to OpenOCD mailing list",
fcfg2_maxaddr0);
+
+ if (fcfg2_pflsh) {
+ if (k_bank->bank_number == 1 && k_chip->maxaddr1_shifted !=
bank->size)
+ LOG_WARNING("MAXADDR1 0x%02" PRIx8 " check failed,"
+ " please report to OpenOCD mailing list",
fcfg2_maxaddr1);
+ } else {
+ if (k_bank->bank_number == first_nvm_bank
+ && k_chip->maxaddr1_shifted !=
k_chip->dflash_size)
+ LOG_WARNING("FlexNVM MAXADDR1 0x%02" PRIx8 " check
failed,"
+ " please report to OpenOCD mailing list",
fcfg2_maxaddr1);
+ }
+
+ return ERROR_OK;
+}
+
static int kinetis_probe(struct flash_bank *bank)
{
int result;
- uint8_t fcfg2_maxaddr0, fcfg2_pflsh, fcfg2_maxaddr1;
unsigned num_blocks, first_nvm_bank;
uint32_t size_k;
struct kinetis_flash_bank *k_bank = bank->driver_priv;
@@ -2780,23 +2819,10 @@ static int kinetis_probe(struct flash_bank *bank)
return ERROR_FLASH_BANK_INVALID;
}
- fcfg2_pflsh = (uint8_t)((k_chip->sim_fcfg2 >> 23) & 0x01);
- fcfg2_maxaddr0 = (uint8_t)((k_chip->sim_fcfg2 >> 24) & 0x7f);
- fcfg2_maxaddr1 = (uint8_t)((k_chip->sim_fcfg2 >> 16) & 0x7f);
-
- if (k_bank->bank_number == 0 && k_chip->fcfg2_maxaddr0_shifted !=
bank->size)
- LOG_WARNING("MAXADDR0 0x%02" PRIx8 " check failed,"
- " please report to OpenOCD mailing list",
fcfg2_maxaddr0);
-
- if (fcfg2_pflsh) {
- if (k_bank->bank_number == 1 && k_chip->fcfg2_maxaddr1_shifted
!= bank->size)
- LOG_WARNING("MAXADDR1 0x%02" PRIx8 " check failed,"
- " please report to OpenOCD mailing list",
fcfg2_maxaddr1);
- } else {
- if (k_bank->bank_number == first_nvm_bank
- && k_chip->fcfg2_maxaddr1_shifted !=
k_chip->dflash_size)
- LOG_WARNING("FlexNVM MAXADDR1 0x%02" PRIx8 " check
failed,"
- " please report to OpenOCD mailing list",
fcfg2_maxaddr1);
+ if (k_chip->bank_verify_maxaddr) {
+ result = k_chip->bank_verify_maxaddr(bank);
+ if (result != ERROR_OK)
+ return result;
}
free(bank->sectors);
--
