This is an automated email from Gerrit.
"Peter Lawrence <majbt...@gmail.com>" just uploaded a new patch set to Gerrit,
which you can find at https://review.openocd.org/c/openocd/+/8020
-- gerrit
commit e6f8ccf5aaf0e5775cc28682edaba87ac95b81c5
Author: Peter Lawrence <majbt...@gmail.com>
Date: Wed Nov 15 09:58:24 2023 -0600
tcl/target/at91sama5d2.cfg: allow choice of SWD instead of JTAG
The target supports both SWD and JTAG, but the existing cfg file
only supports JTAG. Using the standard [using_jtag] mechanism,
the user would now have a choice.
Change-Id: Ic6adb68090422812d591f6bf5b945ac10f323c74
Signed-off-by: Peter Lawrence <majbt...@gmail.com>
diff --git a/tcl/target/at91sama5d2.cfg b/tcl/target/at91sama5d2.cfg
index 65e5217e1e..6dd2370dfa 100644
--- a/tcl/target/at91sama5d2.cfg
+++ b/tcl/target/at91sama5d2.cfg
@@ -1,5 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-or-later
#
+# SAMA5D2 devices support both JTAG and SWD transports.
+#
# The JTAG connection is disabled at reset, and during the ROM Code execution.
# It is re-enabled when the ROM code jumps in the boot file copied from an
# external Flash memory into the internalSRAM, or when the ROM code launches
@@ -12,14 +14,21 @@
# - if enabled, boundary Scan mode is activated. JTAG ID Code value is
0x05B3F03F.
# - if disabled, ICE mode is activated. Debug Port JTAG IDCODE value is
0x5BA00477
#
+
+source [find target/swj-dp.tcl]
+
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME at91sama5d2
}
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \
- -expected-id 0x5ba00477
+if {[using_jtag]} {
+ jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \
+ -expected-id 0x5ba00477
+} else {
+ swd newdap $_CHIPNAME cpu -expected-id 0x5ba00477
+}
# Cortex-A5 target
set _TARGETNAME $_CHIPNAME.cpu_a5
--
