This is an automated email from Gerrit.
"Ian Thompson <ia...@cadence.com>" just uploaded a new patch set to Gerrit,
which you can find at https://review.openocd.org/c/openocd/+/8077
-- gerrit
commit 07e8dba36cfbe0399070ec0144699d4520d7869b
Author: ianst <ia...@cadence.com>
Date: Wed Jan 3 09:53:54 2024 -0800
target/xtensa: add dual-core support
- Example for configuring multiple non-SMP
Xtensa cores, e.g. for heterogeneous debug
- JTAG only at this time; DAP out of scope
- Dual-Xtensa Palladium example via VDebug
Signed-off-by: ianst <ia...@cadence.com>
Change-Id: Iff77970b2ac436309d027bed11ef57000bc5beb9
diff --git a/tcl/board/xtensa-palladium-vdebug-dual.cfg
b/tcl/board/xtensa-palladium-vdebug-dual.cfg
new file mode 100644
index 0000000000..47d56f7607
--- /dev/null
+++ b/tcl/board/xtensa-palladium-vdebug-dual.cfg
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Cadence virtual debug interface
+# for Palladium emulation systems
+#
+
+source [find interface/vdebug.cfg]
+
+# vdebug select JTAG transport
+transport select jtag
+
+# JTAG reset config, frequency and reset delay
+reset_config trst_and_srst
+adapter speed 50000
+adapter srst delay 5
+
+source [find target/vd_xtensa_jtag_dual.cfg]
diff --git a/tcl/target/vd_xtensa_jtag.cfg b/tcl/target/vd_xtensa_jtag.cfg
new file mode 100644
index 0000000000..0d0e04ccf8
--- /dev/null
+++ b/tcl/target/vd_xtensa_jtag.cfg
@@ -0,0 +1,28 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Cadence virtual debug interface for Xtensa processors
+# for Palladium emulation systems
+#
+# Future improvement: Enable backdoor memory access
+# set _MEMSTART 0x00000000
+# set _MEMSIZE 0x100000
+
+# BFM hierarchical path and input clk period
+vdebug bfm_path Testbench.VJTAG 10ns
+
+# DMA Memories to access backdoor (up to 4)
+# vdebug mem_path tbench.u_mcu.u_sys.u_itcm_ram.Mem $_MEMSTART $_MEMSIZE
+
+# Create Xtensa target first
+source [find target/xtensa.cfg]
+
+# Configure Xtensa core parameters next
+# Generate [xtensa-core-XXX.cfg] via "xt-gdb --dump-oocd-config"
+
+# register target
+proc vdebug_examine_end {} {
+# vdebug register_target
+}
+
+# Default hooks
+$_TARGETNAME configure -event examine-end { vdebug_examine_end }
+
diff --git a/tcl/target/vd_xtensa_jtag_dual.cfg
b/tcl/target/vd_xtensa_jtag_dual.cfg
new file mode 100644
index 0000000000..ae25f5dcb4
--- /dev/null
+++ b/tcl/target/vd_xtensa_jtag_dual.cfg
@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Cadence virtual debug interface for Xtensa processors
+# for Palladium emulation systems
+#
+# Future improvement: Enable backdoor memory access
+# set _MEMSTART 0x00000000
+# set _MEMSIZE 0x100000
+
+# BFM hierarchical path and input clk period
+vdebug bfm_path Testbench.VJTAG 10ns
+
+# DMA Memories to access backdoor (up to 4)
+# vdebug mem_path tbench.u_mcu.u_sys.u_itcm_ram.Mem $_MEMSTART $_MEMSIZE
+
+# Create Xtensa target first
+source [find target/xtensa_dual.cfg]
+
+# Configure Xtensa core parameters next
+# Generate [xtensa-core-XXX.cfg] via "xt-gdb --dump-oocd-config"
+
+# register target
+proc vdebug_examine_end {} {
+# vdebug register_target
+}
+
+# Default hooks
+$_TAPNAME0 configure -event examine-end { vdebug_examine_end }
+$_TAPNAME1 configure -event examine-end { vdebug_examine_end }
+
diff --git a/tcl/target/xtensa.cfg b/tcl/target/xtensa.cfg
index 101e13546f..6a4826d7a4 100644
--- a/tcl/target/xtensa.cfg
+++ b/tcl/target/xtensa.cfg
@@ -5,7 +5,7 @@
set xtensa_ids { 0x120034e5 0x120134e5
0x209034e5 0x209134e5 0x209234e5 0x209334e5
0x209434e5 0x209534e5 0x209634e5 0x209734e5
0x20a034e5 0x20a134e5 0x20a234e5 0x20a334e5
0x20a434e5 0x20a534e5 0x20a634e5 0x20a734e5 0x20a834e5
- 0x20b034e5 }
+ 0x20b034e5 0x20b33ac5 0x20b33ac7 }
set expected_xtensa_ids {}
foreach i $xtensa_ids {
lappend expected_xtensa_ids -expected-id $i
diff --git a/tcl/target/xtensa_dual.cfg b/tcl/target/xtensa_dual.cfg
new file mode 100644
index 0000000000..514e10a931
--- /dev/null
+++ b/tcl/target/xtensa_dual.cfg
@@ -0,0 +1,56 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Target Support for Xtensa Processors
+#
+
+set xtensa_ids { 0x120034e5 0x120134e5
+ 0x209034e5 0x209134e5 0x209234e5 0x209334e5
0x209434e5 0x209534e5 0x209634e5 0x209734e5
+ 0x20a034e5 0x20a134e5 0x20a234e5 0x20a334e5
0x20a434e5 0x20a534e5 0x20a634e5 0x20a734e5 0x20a834e5
+ 0x20b034e5 0x20b33ac5 0x20b33ac7 }
+set expected_xtensa_ids {}
+foreach i $xtensa_ids {
+ lappend expected_xtensa_ids -expected-id $i
+}
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME xtensa
+}
+
+if { [info exists CPUTAPID] } {
+ set _CPUTAPARGLIST "-expected-id $CPUTAPID"
+} else {
+ set _CPUTAPARGLIST [join $expected_xtensa_ids]
+}
+
+set _TARGETNAME $_CHIPNAME
+set _CPU0NAME cpu0
+set _CPU1NAME cpu1
+set _TAPNAME0 $_CHIPNAME.$_CPU0NAME
+set _TAPNAME1 $_CHIPNAME.$_CPU1NAME
+
+if { [info exists XTENSA_DAP] } {
+ source [find target/swj-dp.tcl]
+ # SWD mode ignores the -irlen parameter
+ eval swj_newdap $_CHIPNAME cpu -irlen 4 $_CPUTAPARGLIST
+ dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+ set _TARGETNAME $_CHIPNAME.cpu
+ if { [info exists XTENSA_DAP_BASE] } {
+ # Specify fixed offset for accessing XDM via APB behind a DAP
interface
+ target create $_TARGETNAME xtensa -dap $_CHIPNAME.dap -dbgbase
$XTENSA_DAP_BASE
+ } else {
+ target create $_TARGETNAME xtensa -dap $_CHIPNAME.dap
+ }
+} else {
+ # JTAG direct (without DAP)
+ eval jtag newtap $_CHIPNAME $_CPU0NAME -irlen 5 $_CPUTAPARGLIST
+ eval jtag newtap $_CHIPNAME $_CPU1NAME -irlen 5 $_CPUTAPARGLIST
+ target create $_TAPNAME0 xtensa -chain-position $_TAPNAME0 -coreid 0
+ target create $_TAPNAME1 xtensa -chain-position $_TAPNAME1 -coreid 1
+}
+
+$_TAPNAME0 configure -event reset-assert-post { soft_reset_halt }
+$_TAPNAME1 configure -event reset-assert-post { soft_reset_halt }
+
+gdb_report_register_access_error enable
--
