This is an automated email from Gerrit.
"Tomas Vanek <van...@fbl.cz>" just uploaded a new patch set to Gerrit, which
you can find at https://review.openocd.org/c/openocd/+/8115
-- gerrit
commit 1a3e07d7d95ce2bcf854722fffeb12f6e3d0603f
Author: Tomas Vanek <van...@fbl.cz>
Date: Mon Jan 22 21:09:31 2024 +0100
flash/nor/nrf5: handle ERROR_WAIT during nRF53/91 flash erase
Erase is initiated by write to a flash address. The write stalls
the bus until the page erase is finished (takes up to 87ms).
If the adapter does not handle SWD WAIT properly, the following read
in nrf5_wait_for_nvmc() returns ERROR_WAIT.
Wait for fixed time before accessing AP. Not nice, but the only
working solution until all adapters handle SWD WAIT.
If the fixed wait did not suffice, continue the wait loop after a delay.
Signed-off-by: Tomas Vanek <van...@fbl.cz>
Change-Id: I63faf38dad79440a0117ed79930442bd2843c6db
diff --git a/src/flash/nor/nrf5.c b/src/flash/nor/nrf5.c
index db4c4b8552..9aab0b2a04 100644
--- a/src/flash/nor/nrf5.c
+++ b/src/flash/nor/nrf5.c
@@ -375,6 +375,12 @@ static int nrf5_wait_for_nvmc(struct nrf5_info *chip)
do {
res = nrf5_nvmc_read_u32(chip, NRF5_NVMC_READY, &ready);
+ if (res == ERROR_WAIT) {
+ /* The adapter does not handle SWD WAIT properly,
+ * add some delay to reduce number of error messages */
+ alive_sleep(10);
+ continue;
+ }
if (res != ERROR_OK) {
LOG_ERROR("Error waiting NVMC_READY: generic flash
write/erase error (check protection etc...)");
return res;
@@ -1070,6 +1076,13 @@ static int nrf5_erase_page(struct flash_bank *bank,
} else if (chip->features & NRF5_FEATURE_ERASE_BY_FLASH_WR) {
res = target_write_u32(chip->target, bank->base +
sector->offset, 0xffffffff);
+ /* Write to flash address stalls the bus for 87 ms until
+ * page erase finishes! This makes problems if the adapter does
not
+ * handle SWD WAIT properly.
+ * Using a target algo would not help, AP gets unresponsive too.
+ * Neither sending AP ABORT helps, the next AP access stalls
again.
+ * Simply wait long enough before accessing AP again... */
+ alive_sleep(90);
} else {
res = nrf5_nvmc_write_u32(chip, NRF5_NVMC_ERASEPAGE,
sector->offset);
--
