This is an automated email from Gerrit. "N S <nlsh...@yahoo.com>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8121
-- gerrit commit 4545cc2cdbd6bf201eee0ccc1496434dffe19cea Author: N S <nlsh...@yahoo.com> Date: Mon Jan 22 21:47:34 2024 -0800 jtag/drivers: fix reset logic handling in OpenJTAG The OpenJTAG driver behaviour always forces a system reset on jtag_init. The driver was incorrectly assuming that when execute_reset is called with trst set to 1 - perform a software TAP reset, otherwise perform a system reset when trst is 0. The set_state call assumes the that OpenJTAG hardware will perform a software TLR reset if the target state is TAP_RESET. This is not the case: the published VHDL will simply find the shortest path to TLR and not perform a fixed 5 cycle operation with TMS held high. Fix the code to only perform system resets when srst is 1 in execute_reset and to force a software TAP reset operation in set_state when the target state is TAP_RESET. Change-Id: I7e0f76f8491efefff1ccaeb4b1ae16e722d76df4 Signed-off-by: N S <nlsh...@yahoo.com> diff --git a/src/jtag/drivers/openjtag.c b/src/jtag/drivers/openjtag.c index dca27b0a64..387eda64b8 100644 --- a/src/jtag/drivers/openjtag.c +++ b/src/jtag/drivers/openjtag.c @@ -660,14 +660,12 @@ static void openjtag_execute_reset(struct jtag_command *cmd) uint8_t buf = 0x00; - if (cmd->cmd.reset->trst) { - buf = 0x03; - } else { + /* Pull SRST low for 5 TCLK cycles */ + if (cmd->cmd.reset->srst) { buf |= 0x04; buf |= 0x05 << 4; + openjtag_add_byte(buf); } - - openjtag_add_byte(buf); } static void openjtag_execute_sleep(struct jtag_command *cmd) @@ -680,8 +678,14 @@ static void openjtag_set_state(uint8_t openocd_state) uint8_t state = openjtag_get_tap_state(openocd_state); uint8_t buf = 0; - buf = 0x01; - buf |= state << 4; + + if (state != OPENJTAG_TAP_RESET) { + buf = 0x01; + buf |= state << 4; + } else { + /* Force software TLR */ + buf = 0x03; + } openjtag_add_byte(buf); } --