This is an automated email from Gerrit.
"Name of user not set <chris.whee...@narfindustries.com>" just uploaded a new
patch set to Gerrit, which you can find at
https://review.openocd.org/c/openocd/+/8135
-- gerrit
commit a19c12d314f2568f0768cbf79e48ed8ec1b78925
Author: WheelNarf <chris.whee...@narfindustries.com>
Date: Fri Feb 9 09:10:33 2024 -0800
jtag/drivers/imx_gpio: add configurable gpio adddress space size to
accommodate other imx chips. Add reset gpio on jtag config
Change-Id: I66147115ca9638c2c18f97aca4faca66d8a9b550
Signed-off-by: WheelNarf <chris.whee...@narfindustries.com>
diff --git a/src/jtag/drivers/imx_gpio.c b/src/jtag/drivers/imx_gpio.c
index d44b1278c0..3ef1db0868 100644
--- a/src/jtag/drivers/imx_gpio.c
+++ b/src/jtag/drivers/imx_gpio.c
@@ -21,8 +21,9 @@
#define IMX_GPIO_REGS_COUNT 8
static uint32_t imx_gpio_peri_base = IMX_GPIO_BASE;
+static uint32_t imx_gpio_peri_size = IMX_GPIO_SIZE;
-struct imx_gpio_regs {
+typedef struct imx_gpio_regs_t {
uint32_t dr;
uint32_t gdir;
uint32_t psr;
@@ -31,25 +32,48 @@ struct imx_gpio_regs {
uint32_t imr;
uint32_t isr;
uint32_t edge_sel;
-} __attribute__((aligned(IMX_GPIO_SIZE)));
+} imx_gpio_regs;
static int dev_mem_fd;
-static volatile struct imx_gpio_regs *pio_base;
+/* imx_gpio_peri_size is in bytes so using 1 byte pointer to be able to
address arbitrary sizes for different chips */
+static volatile uint8_t *gpio_base = NULL;
+
+/* gpio_base will be cast to imx_gpio_regs* to access fields */
+static volatile imx_gpio_regs *curr_reg = NULL;
+
/* GPIO setup functions */
static inline bool gpio_mode_get(int g)
{
- return pio_base[g / 32].gdir >> (g & 0x1F) & 1;
+ int gpio_num = g >> 5; //Divide by 32
+
+ if(gpio_base && gpio_num < IMX_GPIO_REGS_COUNT) {
+ curr_reg = (imx_gpio_regs*)&gpio_base[gpio_num *
imx_gpio_peri_size];
+ return curr_reg->gdir >> (g & 0x1F) & 1;
+ }
+ else {
+ return 0;
+ }
}
static inline void gpio_mode_input_set(int g)
{
- pio_base[g / 32].gdir &= ~(1u << (g & 0x1F));
+ int gpio_num = g >> 5; //Divide by 32
+
+ if(gpio_base && gpio_num < IMX_GPIO_REGS_COUNT) {
+ curr_reg = (imx_gpio_regs*)&gpio_base[gpio_num *
imx_gpio_peri_size];
+ curr_reg->gdir &= ~(1u << (g & 0x1F));
+ }
}
static inline void gpio_mode_output_set(int g)
{
- pio_base[g / 32].gdir |= (1u << (g & 0x1F));
+ int gpio_num = g >> 5; //Divide by 32
+
+ if(gpio_base && gpio_num < IMX_GPIO_REGS_COUNT) {
+ curr_reg = (imx_gpio_regs*)&gpio_base[gpio_num *
imx_gpio_peri_size];
+ curr_reg->gdir |= (1u << (g & 0x1F));
+ }
}
static inline void gpio_mode_set(int g, int m)
@@ -59,17 +83,35 @@ static inline void gpio_mode_set(int g, int m)
static inline void gpio_set(int g)
{
- pio_base[g / 32].dr |= (1u << (g & 0x1F));
+ int gpio_num = g >> 5; //Divide by 32
+
+ if(gpio_base && gpio_num < IMX_GPIO_REGS_COUNT) {
+ curr_reg = (imx_gpio_regs*)&gpio_base[gpio_num *
imx_gpio_peri_size];
+ curr_reg->dr |= (1u << (g & 0x1F));
+ }
}
static inline void gpio_clear(int g)
{
- pio_base[g / 32].dr &= ~(1u << (g & 0x1F));
+ int gpio_num = g >> 5; //Divide by 32
+
+ if(gpio_base && gpio_num < IMX_GPIO_REGS_COUNT) {
+ curr_reg = (imx_gpio_regs*)&gpio_base[gpio_num * imx_gpio_peri_size];
+ curr_reg->dr &= ~(1u << (g & 0x1F));
+ }
}
static inline bool gpio_level(int g)
{
- return pio_base[g / 32].dr >> (g & 0x1F) & 1;
+ int gpio_num = g >> 5; //Divide by 32
+
+ if(gpio_base && gpio_num < IMX_GPIO_REGS_COUNT) {
+ curr_reg = (imx_gpio_regs*)&gpio_base[gpio_num *
imx_gpio_peri_size];
+ return curr_reg->dr >> (g & 0x1F) & 1;
+ }
+ else {
+ return 0;
+ }
}
static bb_value_t imx_gpio_read(void);
@@ -202,18 +244,20 @@ static int is_gpio_valid(int gpio)
COMMAND_HANDLER(imx_gpio_handle_jtag_gpionums)
{
- if (CMD_ARGC == 4) {
+ if (CMD_ARGC == 5) {
COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], tck_gpio);
COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], tms_gpio);
COMMAND_PARSE_NUMBER(int, CMD_ARGV[2], tdi_gpio);
COMMAND_PARSE_NUMBER(int, CMD_ARGV[3], tdo_gpio);
+ COMMAND_PARSE_NUMBER(int, CMD_ARGV[4], srst_gpio);
+
} else if (CMD_ARGC != 0) {
return ERROR_COMMAND_SYNTAX_ERROR;
}
command_print(CMD,
- "imx_gpio GPIO config: tck = %d, tms = %d, tdi = %d,
tdo = %d",
- tck_gpio, tms_gpio, tdi_gpio, tdo_gpio);
+ "imx_gpio GPIO config: tck = %d, tms = %d, tdi = %d,
tdo = %d, srst = %d",
+ tck_gpio, tms_gpio, tdi_gpio, tdo_gpio, srst_gpio);
return ERROR_OK;
}
@@ -328,6 +372,16 @@ COMMAND_HANDLER(imx_gpio_handle_peripheral_base)
return ERROR_OK;
}
+COMMAND_HANDLER(imx_gpio_handle_peripheral_size)
+{
+ if (CMD_ARGC == 1)
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], imx_gpio_peri_size);
+
+ command_print(CMD, "imx_gpio: peripheral_size = 0x%08x",
+ imx_gpio_peri_size);
+ return ERROR_OK;
+}
+
static const struct command_registration imx_gpio_command_handlers[] = {
{
.name = "imx_gpio_jtag_nums",
@@ -413,6 +467,13 @@ static const struct command_registration
imx_gpio_command_handlers[] = {
.help = "peripheral base to access GPIOs (0x0209c000 for most
IMX).",
.usage = "[base]",
},
+ {
+ .name = "imx_gpio_peripheral_size",
+ .handler = &imx_gpio_handle_peripheral_size,
+ .mode = COMMAND_CONFIG,
+ .help = "peripheral size of GPIOs (0x00004000 for most IMX).",
+ .usage = "[size]",
+ },
COMMAND_REGISTRATION_DONE
};
@@ -485,12 +546,12 @@ static int imx_gpio_init(void)
}
LOG_INFO("imx_gpio mmap: pagesize: %u, regionsize: %u",
- (unsigned int) sysconf(_SC_PAGE_SIZE),
IMX_GPIO_REGS_COUNT * IMX_GPIO_SIZE);
- pio_base = mmap(NULL, IMX_GPIO_REGS_COUNT * IMX_GPIO_SIZE,
+ (unsigned int) sysconf(_SC_PAGE_SIZE),
IMX_GPIO_REGS_COUNT * imx_gpio_peri_size);
+ gpio_base = mmap(NULL, IMX_GPIO_REGS_COUNT * imx_gpio_peri_size,
PROT_READ | PROT_WRITE,
MAP_SHARED, dev_mem_fd, imx_gpio_peri_base);
- if (pio_base == MAP_FAILED) {
+ if (gpio_base == MAP_FAILED) {
LOG_ERROR("mmap: %s", strerror(errno));
close(dev_mem_fd);
return ERROR_JTAG_INIT_FAILED;
--
