This is an automated email from Gerrit.
"Name of user not set <chris.whee...@narfindustries.com>" just uploaded a new
patch set to Gerrit, which you can find at
https://review.openocd.org/c/openocd/+/8139
-- gerrit
commit 64bfabe0a752813a02800d23c570a38f5fa45e72
Author: WheelNarf <chris.whee...@narfindustries.com>
Date: Mon Feb 12 09:54:13 2024 -0800
jtag/drivers/imx_gpio: add configurable gpio address space size to
accommodate other imx chips. Instead of checking each GPIO usage for range,
only check on init. Using offsets via defines instead of struct to address
individual registers
Change-Id: I5f4b29f8957e873b500913633b3ae545a08b8986
Signed-off-by: WheelNarf <chris.whee...@narfindustries.com>
diff --git a/src/jtag/drivers/imx_gpio.c b/src/jtag/drivers/imx_gpio.c
index 3ef1db0868..7227899860 100644
--- a/src/jtag/drivers/imx_gpio.c
+++ b/src/jtag/drivers/imx_gpio.c
@@ -20,60 +20,37 @@
#define IMX_GPIO_SIZE 0x00004000
#define IMX_GPIO_REGS_COUNT 8
+#define IMX_GPIO_REGS_DR (sizeof(uint32_t) * 0)
+#define IMX_GPIO_REGS_GDIR (sizeof(uint32_t) * 1)
+#define IMX_GPIO_REGS_PSR (sizeof(uint32_t) * 1)
+#define IMX_GPIO_REGS_ICR1 (sizeof(uint32_t) * 1)
+#define IMX_GPIO_REGS_ICR2 (sizeof(uint32_t) * 1)
+#define IMX_GPIO_REGS_IMR (sizeof(uint32_t) * 1)
+#define IMX_GPIO_REGS_ISR (sizeof(uint32_t) * 1)
+#define IMX_GPIO_REGS_EDGE_SEL (sizeof(uint32_t) * 1)
+
static uint32_t imx_gpio_peri_base = IMX_GPIO_BASE;
static uint32_t imx_gpio_peri_size = IMX_GPIO_SIZE;
-typedef struct imx_gpio_regs_t {
- uint32_t dr;
- uint32_t gdir;
- uint32_t psr;
- uint32_t icr1;
- uint32_t icr2;
- uint32_t imr;
- uint32_t isr;
- uint32_t edge_sel;
-} imx_gpio_regs;
-
static int dev_mem_fd;
/* imx_gpio_peri_size is in bytes so using 1 byte pointer to be able to
address arbitrary sizes for different chips */
-static volatile uint8_t *gpio_base = NULL;
+static volatile uint8_t *pio_base = 0;
-/* gpio_base will be cast to imx_gpio_regs* to access fields */
-static volatile imx_gpio_regs *curr_reg = NULL;
-
/* GPIO setup functions */
static inline bool gpio_mode_get(int g)
{
- int gpio_num = g >> 5; //Divide by 32
-
- if(gpio_base && gpio_num < IMX_GPIO_REGS_COUNT) {
- curr_reg = (imx_gpio_regs*)&gpio_base[gpio_num *
imx_gpio_peri_size];
- return curr_reg->gdir >> (g & 0x1F) & 1;
- }
- else {
- return 0;
- }
+ return pio_base[(g / 32) * imx_gpio_peri_size + IMX_GPIO_REGS_GDIR] >>
(g & 0x1F) & 1;
}
static inline void gpio_mode_input_set(int g)
{
- int gpio_num = g >> 5; //Divide by 32
-
- if(gpio_base && gpio_num < IMX_GPIO_REGS_COUNT) {
- curr_reg = (imx_gpio_regs*)&gpio_base[gpio_num *
imx_gpio_peri_size];
- curr_reg->gdir &= ~(1u << (g & 0x1F));
- }
+ pio_base[(g / 32) * imx_gpio_peri_size + IMX_GPIO_REGS_GDIR] &= ~(1u
<< (g & 0x1F));
}
static inline void gpio_mode_output_set(int g)
{
- int gpio_num = g >> 5; //Divide by 32
-
- if(gpio_base && gpio_num < IMX_GPIO_REGS_COUNT) {
- curr_reg = (imx_gpio_regs*)&gpio_base[gpio_num *
imx_gpio_peri_size];
- curr_reg->gdir |= (1u << (g & 0x1F));
- }
+ pio_base[(g / 32) * imx_gpio_peri_size + IMX_GPIO_REGS_GDIR] |= (1u <<
(g & 0x1F));
}
static inline void gpio_mode_set(int g, int m)
@@ -83,35 +60,17 @@ static inline void gpio_mode_set(int g, int m)
static inline void gpio_set(int g)
{
- int gpio_num = g >> 5; //Divide by 32
-
- if(gpio_base && gpio_num < IMX_GPIO_REGS_COUNT) {
- curr_reg = (imx_gpio_regs*)&gpio_base[gpio_num *
imx_gpio_peri_size];
- curr_reg->dr |= (1u << (g & 0x1F));
- }
+ pio_base[(g / 32) * imx_gpio_peri_size + IMX_GPIO_REGS_DR] |= (1u <<
(g & 0x1F));
}
static inline void gpio_clear(int g)
{
- int gpio_num = g >> 5; //Divide by 32
-
- if(gpio_base && gpio_num < IMX_GPIO_REGS_COUNT) {
- curr_reg = (imx_gpio_regs*)&gpio_base[gpio_num * imx_gpio_peri_size];
- curr_reg->dr &= ~(1u << (g & 0x1F));
- }
+ pio_base[(g /32) * imx_gpio_peri_size + IMX_GPIO_REGS_DR] &= ~(1u << (g &
0x1F));
}
static inline bool gpio_level(int g)
{
- int gpio_num = g >> 5; //Divide by 32
-
- if(gpio_base && gpio_num < IMX_GPIO_REGS_COUNT) {
- curr_reg = (imx_gpio_regs*)&gpio_base[gpio_num *
imx_gpio_peri_size];
- return curr_reg->dr >> (g & 0x1F) & 1;
- }
- else {
- return 0;
- }
+ return pio_base[(g / 32) * imx_gpio_peri_size + IMX_GPIO_REGS_DR] >> (g
& 0x1F) & 1;
}
static bb_value_t imx_gpio_read(void);
@@ -244,20 +203,18 @@ static int is_gpio_valid(int gpio)
COMMAND_HANDLER(imx_gpio_handle_jtag_gpionums)
{
- if (CMD_ARGC == 5) {
+ if (CMD_ARGC == 4) {
COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], tck_gpio);
COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], tms_gpio);
COMMAND_PARSE_NUMBER(int, CMD_ARGV[2], tdi_gpio);
COMMAND_PARSE_NUMBER(int, CMD_ARGV[3], tdo_gpio);
- COMMAND_PARSE_NUMBER(int, CMD_ARGV[4], srst_gpio);
-
} else if (CMD_ARGC != 0) {
return ERROR_COMMAND_SYNTAX_ERROR;
}
command_print(CMD,
- "imx_gpio GPIO config: tck = %d, tms = %d, tdi = %d,
tdo = %d, srst = %d",
- tck_gpio, tms_gpio, tdi_gpio, tdo_gpio, srst_gpio);
+ "imx_gpio GPIO config: tck = %d, tms = %d, tdi = %d,
tdo = %d",
+ tck_gpio, tms_gpio, tdi_gpio, tdo_gpio);
return ERROR_OK;
}
@@ -533,6 +490,15 @@ static int imx_gpio_init(void)
LOG_ERROR("Require tck, tms, tdi and tdo gpios for JTAG mode");
return ERROR_JTAG_INIT_FAILED;
}
+
+ if(transport_is_jtag()) {
+ if( tck_gpio / 32 >= IMX_GPIO_REGS_COUNT ||
+ tms_gpio / 32 >= IMX_GPIO_REGS_COUNT ||
+ tdi_gpio / 32 >= IMX_GPIO_REGS_COUNT ||
+ tdo_gpio / 32 >= IMX_GPIO_REGS_COUNT ) {
+ return ERROR_JTAG_INIT_FAILED;
+ }
+ }
if (transport_is_swd() && !imx_gpio_swd_mode_possible()) {
LOG_ERROR("Require swclk and swdio gpio for SWD mode");
@@ -547,11 +513,11 @@ static int imx_gpio_init(void)
LOG_INFO("imx_gpio mmap: pagesize: %u, regionsize: %u",
(unsigned int) sysconf(_SC_PAGE_SIZE),
IMX_GPIO_REGS_COUNT * imx_gpio_peri_size);
- gpio_base = mmap(NULL, IMX_GPIO_REGS_COUNT * imx_gpio_peri_size,
+ pio_base = mmap(NULL, IMX_GPIO_REGS_COUNT * imx_gpio_peri_size,
PROT_READ | PROT_WRITE,
MAP_SHARED, dev_mem_fd, imx_gpio_peri_base);
- if (gpio_base == MAP_FAILED) {
+ if (pio_base == MAP_FAILED) {
LOG_ERROR("mmap: %s", strerror(errno));
close(dev_mem_fd);
return ERROR_JTAG_INIT_FAILED;
--
