This is an automated email from Gerrit.
"Name of user not set <chris.whee...@narfindustries.com>" just uploaded a new
patch set to Gerrit, which you can find at
https://review.openocd.org/c/openocd/+/8158
-- gerrit
commit 46b25ae8768ff0b441eca7264654e53f39f29e39
Author: WheelNarf <chris.whee...@narfindustries.com>
Date: Thu Feb 22 08:13:03 2024 -0800
jtag/drivers/imx_gpio: imx configurable gpio address space size
The current gpio address space size is hard coded at 0x00004000 bytes,
not all imx chips use this size. This patch adds imx_gpio_peri_size as
an option in the config file for the interface.
Signed-off-by: WheelNarf <chris.whee...@narfindustries.com>
Change-Id: I93a9df89388b68cab22cb5f2c742e074c2fa77a6
diff --git a/src/jtag/drivers/imx_gpio.c b/src/jtag/drivers/imx_gpio.c
index d44b1278c0..489199733e 100644
--- a/src/jtag/drivers/imx_gpio.c
+++ b/src/jtag/drivers/imx_gpio.c
@@ -20,36 +20,50 @@
#define IMX_GPIO_SIZE 0x00004000
#define IMX_GPIO_REGS_COUNT 8
-static uint32_t imx_gpio_peri_base = IMX_GPIO_BASE;
+#define IMX_GPIO_REGS_DR (sizeof(uint32_t) * 0)
+#define IMX_GPIO_REGS_GDIR (sizeof(uint32_t) * 1)
+#define IMX_GPIO_REGS_PSR (sizeof(uint32_t) * 2)
+#define IMX_GPIO_REGS_ICR1 (sizeof(uint32_t) * 3)
+#define IMX_GPIO_REGS_ICR2 (sizeof(uint32_t) * 4)
+#define IMX_GPIO_REGS_IMR (sizeof(uint32_t) * 5)
+#define IMX_GPIO_REGS_ISR (sizeof(uint32_t) * 6)
+#define IMX_GPIO_REGS_EDGE_SEL (sizeof(uint32_t) * 7)
+
+/* GPIO setup macros */
+#define IMX_GPIO_REG_READ(g, offset) \
+ (*(pio_base + (((g) / 32) * imx_gpio_peri_size + (offset)) /
sizeof(uint32_t)))
+
+#define IMX_GPIO_REG_WRITE(g, offset, value) \
+ (*(pio_base + (((g) / 32) * imx_gpio_peri_size + (offset)) /
sizeof(uint32_t)) = (value))
-struct imx_gpio_regs {
- uint32_t dr;
- uint32_t gdir;
- uint32_t psr;
- uint32_t icr1;
- uint32_t icr2;
- uint32_t imr;
- uint32_t isr;
- uint32_t edge_sel;
-} __attribute__((aligned(IMX_GPIO_SIZE)));
+#define IMX_GPIO_SET_REG_BITS(g, offset, bit_mask) \
+ (*(pio_base + (((g) / 32) * imx_gpio_peri_size + (offset)) /
sizeof(uint32_t)) |= (bit_mask))
+
+#define IMX_GPIO_CLEAR_REG_BITS(g, offset, bit_mask) \
+ (*(pio_base + (((g) / 32) * imx_gpio_peri_size + (offset)) /
sizeof(uint32_t)) &= ~(bit_mask))
+
+static uint32_t imx_gpio_peri_base = IMX_GPIO_BASE;
+static uint32_t imx_gpio_peri_size = IMX_GPIO_SIZE;
static int dev_mem_fd;
-static volatile struct imx_gpio_regs *pio_base;
+
+/* imx_gpio_peri_size is in bytes so using 1 byte pointer to be able to
address arbitrary sizes for different chips */
+static volatile uint32_t *pio_base;
/* GPIO setup functions */
static inline bool gpio_mode_get(int g)
{
- return pio_base[g / 32].gdir >> (g & 0x1F) & 1;
+ return IMX_GPIO_REG_READ(g, IMX_GPIO_REGS_GDIR) >> (g & 0x1F) & 1;
}
static inline void gpio_mode_input_set(int g)
{
- pio_base[g / 32].gdir &= ~(1u << (g & 0x1F));
+ IMX_GPIO_CLEAR_REG_BITS(g, IMX_GPIO_REGS_GDIR, 1u << (g & 0x1F));
}
static inline void gpio_mode_output_set(int g)
{
- pio_base[g / 32].gdir |= (1u << (g & 0x1F));
+ IMX_GPIO_SET_REG_BITS(g, IMX_GPIO_REGS_GDIR, 1u << (g & 0x1F));
}
static inline void gpio_mode_set(int g, int m)
@@ -59,17 +73,17 @@ static inline void gpio_mode_set(int g, int m)
static inline void gpio_set(int g)
{
- pio_base[g / 32].dr |= (1u << (g & 0x1F));
+ IMX_GPIO_SET_REG_BITS(g, IMX_GPIO_REGS_DR, 1u << (g & 0x1F));
}
static inline void gpio_clear(int g)
{
- pio_base[g / 32].dr &= ~(1u << (g & 0x1F));
+ IMX_GPIO_CLEAR_REG_BITS(g, IMX_GPIO_REGS_DR, 1u << (g & 0x1F));
}
static inline bool gpio_level(int g)
{
- return pio_base[g / 32].dr >> (g & 0x1F) & 1;
+ return IMX_GPIO_REG_READ(g, IMX_GPIO_REGS_DR) >> (g & 0x1F) & 1;
}
static bb_value_t imx_gpio_read(void);
@@ -211,6 +225,15 @@ COMMAND_HANDLER(imx_gpio_handle_jtag_gpionums)
return ERROR_COMMAND_SYNTAX_ERROR;
}
+ if (tck_gpio / 32 >= IMX_GPIO_REGS_COUNT)
+ return ERROR_JTAG_INIT_FAILED;
+ if (tms_gpio / 32 >= IMX_GPIO_REGS_COUNT)
+ return ERROR_JTAG_INIT_FAILED;
+ if (tdi_gpio / 32 >= IMX_GPIO_REGS_COUNT)
+ return ERROR_JTAG_INIT_FAILED;
+ if (tdo_gpio / 32 >= IMX_GPIO_REGS_COUNT)
+ return ERROR_JTAG_INIT_FAILED;
+
command_print(CMD,
"imx_gpio GPIO config: tck = %d, tms = %d, tdi = %d,
tdo = %d",
tck_gpio, tms_gpio, tdi_gpio, tdo_gpio);
@@ -328,6 +351,16 @@ COMMAND_HANDLER(imx_gpio_handle_peripheral_base)
return ERROR_OK;
}
+COMMAND_HANDLER(imx_gpio_handle_peripheral_size)
+{
+ if (CMD_ARGC == 1)
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], imx_gpio_peri_size);
+
+ command_print(CMD, "imx_gpio: peripheral_size = 0x%08x",
+ imx_gpio_peri_size);
+ return ERROR_OK;
+}
+
static const struct command_registration imx_gpio_command_handlers[] = {
{
.name = "imx_gpio_jtag_nums",
@@ -413,6 +446,13 @@ static const struct command_registration
imx_gpio_command_handlers[] = {
.help = "peripheral base to access GPIOs (0x0209c000 for most
IMX).",
.usage = "[base]",
},
+ {
+ .name = "imx_gpio_peripheral_size",
+ .handler = &imx_gpio_handle_peripheral_size,
+ .mode = COMMAND_CONFIG,
+ .help = "peripheral size of GPIOs (0x00004000 for most IMX).",
+ .usage = "[size]",
+ },
COMMAND_REGISTRATION_DONE
};
@@ -485,8 +525,8 @@ static int imx_gpio_init(void)
}
LOG_INFO("imx_gpio mmap: pagesize: %u, regionsize: %u",
- (unsigned int) sysconf(_SC_PAGE_SIZE),
IMX_GPIO_REGS_COUNT * IMX_GPIO_SIZE);
- pio_base = mmap(NULL, IMX_GPIO_REGS_COUNT * IMX_GPIO_SIZE,
+ (unsigned int) sysconf(_SC_PAGE_SIZE),
IMX_GPIO_REGS_COUNT * imx_gpio_peri_size);
+ pio_base = mmap(NULL, IMX_GPIO_REGS_COUNT * imx_gpio_peri_size,
PROT_READ | PROT_WRITE,
MAP_SHARED, dev_mem_fd, imx_gpio_peri_base);
--
