[PATCH]: 2d038796aa tcl/board: Add support for Terasic DE1-SoC tcl/target: Add support for connecting via the FPGA JTAG chain

[gerrit]

This is an automated email from Gerrit.

"Flemming Richter <f...@emlogic.no>" just uploaded a new patch set to Gerrit, 
which you can find at https://review.openocd.org/c/openocd/+/8175

-- gerrit

commit 2d038796aaffd559e90337a11bf70cd52e7f4a4a
Author: Flemming Richter <f...@emlogic.no>
Date:   Tue Mar 12 12:01:03 2024 +0100

    tcl/board: Add support for Terasic DE1-SoC
    tcl/target: Add support for connecting via the FPGA JTAG chain
    
    The altera_fpgasoc.cfg assumes that the JTAG connector
    is connected to the CPU JTAG, but for Terasic DE1-SoC,
    the JTAG connector (which is available via the USB B
    plug on the board) is connected to the FPGA JTAG.
    Because of that, we need to add a check in
    altera_fpgasoc.cfg on which JTAG chain to use.
    
    Change-Id: I26043ba6449102fd898d23752341db66aa25596e
    Signed-off-by: Flemming Richter <f...@emlogic.no>

diff --git a/tcl/board/terasic-de1-soc.cfg b/tcl/board/terasic-de1-soc.cfg
new file mode 100644
index 0000000000..972aaba1d3
--- /dev/null
+++ b/tcl/board/terasic-de1-soc.cfg
@@ -0,0 +1,31 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Support for the following board:
+# 
https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=205&No=836&PartNo=1
+
+set FPGA_TAPID 0x02d120dd
+set DAP_TAPID 0x4ba00477
+set JTAG_IS_CONNECTED_TO_FPGA_TAP 1
+source [find interface/altera-usb-blaster2.cfg]
+source [find target/altera_fpgasoc.cfg]
+
+gdb_memory_map enable
+gdb_flash_program enable
+gdb_report_data_abort enable
+gdb_report_register_access_error enable
+gdb_port 3333
+
+proc _apu_up {} {
+       set _current_target [target current]
+       set _current_type [${_current_target} cget -type]
+       ${_current_target} arp_examine
+       cortex_a smp off
+}
+
+echo {Adding post_init_commands}
+lappend post_init_commands {echo "OpenOCD successfully initialized"}
+lappend post_init_commands {_apu_up}
+lappend post_init_commands {echo "Configured cores"}
+lappend post_init_commands {fpgasoc.cpu.0 cortex_a smp off}
+lappend post_init_commands {fpgasoc.cpu.0 cortex_a dbginit}
+
diff --git a/tcl/target/altera_fpgasoc.cfg b/tcl/target/altera_fpgasoc.cfg
index a98b346c6c..59a30fada0 100644
--- a/tcl/target/altera_fpgasoc.cfg
+++ b/tcl/target/altera_fpgasoc.cfg
@@ -4,28 +4,35 @@
 # Altera cyclone V SoC family, 5Cxxx
 #
 if { [info exists CHIPNAME] } {
-   set _CHIPNAME $CHIPNAME
+       set _CHIPNAME $CHIPNAME
 } else {
-   set _CHIPNAME fpgasoc
+       set _CHIPNAME fpgasoc
 }
 
 # CoreSight Debug Access Port
+if { [info exists FPGA_TAPID] } {
+       set _FPGA_TAPID $FPGA_TAPID
+} else {
+       set _FPGA_TAPID 0x02d020dd
+}
 if { [info exists DAP_TAPID] } {
         set _DAP_TAPID $DAP_TAPID
 } else {
         set _DAP_TAPID 0x4ba00477
 }
 
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \
-        -expected-id $_DAP_TAPID
-
-# Subsidiary TAP: fpga
-if { [info exists FPGA_TAPID] } {
-   set _FPGA_TAPID $FPGA_TAPID
+if { [info exists JTAG_IS_CONNECTED_TO_FPGA_TAP] } {
+       jtag newtap $_CHIPNAME.fpga tap -irlen 10 -ircapture 0x01 \
+                    -irmask 0x3 -expected-id $_FPGA_TAPID
+       jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 \
+                    -irmask 0x0f -expected-id $_DAP_TAPID
 } else {
-   set _FPGA_TAPID 0x02d020dd
+       jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 \
+                    -irmask 0x0f -expected-id $_DAP_TAPID
+       jtag newtap $_CHIPNAME.fpga tap -irlen 10 -ircapture 0x01 \
+                    -irmask 0x3 -expected-id $_FPGA_TAPID
 }
-jtag newtap $_CHIPNAME.fpga tap -irlen 10 -ircapture 0x01 -irmask 0x3 
-expected-id $_FPGA_TAPID
+# Subsidiary TAP: fpga
 
 
 #

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