This is an automated email from Gerrit.
"Alexandre Bailon <abai...@baylibre.com>" just uploaded a new patch set to
Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8192
-- gerrit
commit 5b9b1d5c76bf5a07ef5c5de305d4765ac0b1e9f5
Author: Alexandre Bailon <abai...@baylibre.com>
Date: Fri Mar 29 21:13:17 2024 +0100
flash/nor: Update cc26xx flash driver to support cc13x2x7
This updates the flash driver to support more than one bank.
This is required to support the cc1352p7 which has two banks.
This only have been tested on a cc1352p7.
The loader has been built using a gcc-arm-none-eabi-4_8-2014q3
toolchain.
Change-Id: Ia813421ececd96d6e2fd4dae910ad60fcc3d3c88
Signed-off-by: Alexandre Bailon <abai...@baylibre.com>
diff --git a/contrib/loaders/flash/cc26xx/cc26x0_algo.inc
b/contrib/loaders/flash/cc26xx/cc26x0_algo.inc
index 2246a36706..4dc4403834 100644
--- a/contrib/loaders/flash/cc26xx/cc26x0_algo.inc
+++ b/contrib/loaders/flash/cc26xx/cc26x0_algo.inc
@@ -1,249 +1,261 @@
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+0x88,0x35,0xed,0x18,0xc6,0x20,0xc4,0x23,0x01,0x36,0x5b,0x00,0x40,0x00,0xb6,0x00,
+0x9b,0x46,0x82,0x46,0x46,0x44,0xc3,0x44,0xc2,0x44,0x08,0xe0,0x2b,0x1c,0x80,0x33,
+0x1b,0x68,0xbb,0x42,0x05,0xd0,0x04,0x3d,0x04,0x3e,0x01,0x3c,0x29,0xd3,0x00,0x2f,
+0xf4,0xd1,0x41,0x46,0x4a,0x68,0x01,0x3a,0x33,0x68,0xa2,0x42,0x30,0xd0,0x00,0x22,
+0x32,0x60,0x00,0x2b,0xef,0xd0,0x40,0x46,0x59,0x46,0x40,0x68,0x01,0x22,0x09,0x68,
+0xa2,0x40,0x00,0x90,0x11,0x42,0x20,0xd0,0x50,0x46,0x00,0x68,0x10,0x42,0x21,0xd1,
+0x02,0x98,0x29,0x68,0x00,0xf0,0x40,0xf8,0x41,0x46,0x49,0x68,0x00,0x9a,0x91,0x42,
+0xb7,0xd1,0x4a,0x46,0x12,0x68,0x42,0x45,0xb3,0xd1,0x04,0x3d,0x04,0x3e,0x01,0x3c,
+0xd5,0xd2,0x18,0x4a,0x00,0x2a,0x11,0xd1,0x05,0xb0,0x3c,0xbc,0x90,0x46,0x99,0x46,
+0xa2,0x46,0xab,0x46,0xf0,0xbc,0x01,0xbc,0x00,0x47,0x00,0xf0,0x25,0xf8,0xe3,0xe7,
+0x4c,0x60,0xce,0xe7,0x28,0x68,0x00,0xf0,0x1f,0xf8,0xdd,0xe7,0x43,0x46,0x5b,0x68,
+0x40,0x46,0x00,0x2b,0x0d,0xd1,0x03,0x68,0x00,0x2b,0x0e,0xd0,0x49,0x46,0x0b,0x60,
+0xaf,0xf3,0x00,0x80,0x4b,0x46,0x1a,0x68,0x90,0x46,0x41,0x46,0x00,0x29,0x91,0xd1,
+0xda,0xe7,0x03,0x68,0xc1,0x46,0x98,0x46,0xf7,0xe7,0x00,0x23,0xfa,0xe7,0xc0,0x46,
+0xcc,0x0f,0x00,0x20,0x00,0x00,0x00,0x00,0x18,0x47,0xc0,0x46,0x08,0xb5,0x01,0x1c,
+0x00,0x22,0x00,0x20,0x00,0x23,0x00,0xf0,0x1f,0xf8,0x08,0xbc,0x02,0xbc,0x08,0x47,
+0x38,0xb5,0x0a,0x4b,0x0a,0x4d,0xed,0x1a,0xad,0x10,0x0a,0xd0,0x01,0x3d,0xac,0x00,
+0xe4,0x18,0x00,0xe0,0x01,0x3d,0x23,0x68,0x00,0xf0,0x0c,0xf8,0x04,0x3c,0x00,0x2d,
+0xf8,0xd1,0x00,0xf0,0x71,0xf8,0x38,0xbc,0x01,0xbc,0x00,0x47,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x18,0x47,0xc0,0x46,0xf0,0xb5,0x4f,0x46,0x46,0x46,0xc0,0xb4,
+0x98,0x46,0x2c,0x4b,0xa4,0x25,0x1b,0x68,0x6d,0x00,0x5c,0x59,0x83,0xb0,0x06,0x1c,
+0x0f,0x1c,0x91,0x46,0x01,0x93,0x00,0x2c,0x46,0xd0,0x65,0x68,0x1f,0x2d,0x1a,0xdd,
+0x25,0x4b,0x00,0x2b,0x02,0xd1,0x01,0x20,0x40,0x42,0x1c,0xe0,0xc8,0x20,0x40,0x00,
+0xaf,0xf3,0x00,0x80,0x04,0x1e,0xf6,0xd0,0x00,0x25,0x45,0x60,0xa4,0x23,0x01,0x98,
+0x5b,0x00,0xc0,0x58,0x01,0x99,0x20,0x60,0xcc,0x50,0xc4,0x23,0x5b,0x00,0xe5,0x50,
+0xc6,0x23,0x5b,0x00,0xe5,0x50,0x00,0x2e,0x0c,0xd1,0x6b,0x1c,0x02,0x35,0xad,0x00,
+0x63,0x60,0x2f,0x51,0x00,0x20,0x03,0xb0,0x0c,0xbc,0x90,0x46,0x99,0x46,0xf0,0xbc,
+0x02,0xbc,0x08,0x47,0xab,0x00,0xe3,0x18,0x88,0x22,0x48,0x46,0x98,0x50,0xc4,0x20,
+0x40,0x00,0x22,0x18,0x10,0x68,0x01,0x21,0xa9,0x40,0x08,0x43,0x10,0x60,0x84,0x22,
+0x52,0x00,0x40,0x46,0x98,0x50,0x02,0x2e,0xdf,0xd1,0xc6,0x22,0x52,0x00,0xa3,0x18,
+0x18,0x68,0x01,0x43,0x19,0x60,0xd8,0xe7,0x1c,0x1c,0x4d,0x34,0xff,0x34,0x5c,0x51,
+0xb3,0xe7,0xc0,0x46,0xcc,0x0f,0x00,0x20,0x00,0x00,0x00,0x00,0xf8,0xb5,0xc0,0x46,
+0xf8,0xbc,0x08,0xbc,0x9e,0x46,0x70,0x47,0xf8,0xb5,0xc0,0x46,0xf8,0xbc,0x08,0xbc,
+0x9e,0x46,0x70,0x47,0x00,0x00,0x00,0x00,0xf8,0xf0,0xff,0x7f,0x01,0x00,0x00,0x00,
+0xe8,0x15,0x00,0x20,0xff,0xff,0xff,0xc5,0xff,0xff,0xff,0xff,0xc5,0xff,0xff,0xff,
+0xc5,0xc5,0xc5,0xff,0xc5,0xc5,0xc5,0xff,0x43,0x00,0x00,0x00,0xd8,0x0f,0x00,0x20,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xc4,0x12,0x00,0x20,
+0x2c,0x13,0x00,0x20,0x94,0x13,0x00,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xc8,0x0f,0x00,0x20,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
@@ -307,20 +319,8 @@
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-0x18,0x0f,0x00,0x20,0xc1,0x00,0x00,0x20,0x91,0x00,0x00,0x20,0x00,0x00,0x00,0x00,
-0x95,0x0d,0x00,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0xd8,0x0f,0x00,0x20,0x61,0x00,0x00,0x20,0x35,0x00,0x00,0x20,0x00,0x00,0x00,0x00,
+0x39,0x0d,0x00,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
diff --git a/contrib/loaders/flash/cc26xx/cc26x2_algo.inc
b/contrib/loaders/flash/cc26xx/cc26x2_algo.inc
index 9adb919f4e..7ba3fca70b 100644
--- a/contrib/loaders/flash/cc26xx/cc26x2_algo.inc
+++ b/contrib/loaders/flash/cc26xx/cc26x2_algo.inc
@@ -1,249 +1,261 @@
/* Autogenerated with ../../../../src/helper/bin2char.sh */
0x08,0xb5,0x00,0xbf,0x00,0xbf,0x00,0xbf,0x00,0xbf,0xdf,0xf8,0x1c,0xd0,0x07,0x48,
-0x07,0x49,0x4f,0xf0,0x00,0x02,0x88,0x42,0xb8,0xbf,0x40,0xf8,0x04,0x2b,0xfa,0xdb,
-0x00,0xf0,0xa8,0xf9,0xfe,0xe7,0x00,0x00,0xf0,0x0e,0x00,0x20,0x54,0x13,0x00,0x20,
-0xfc,0x13,0x00,0x20,0x08,0xb5,0x07,0x4b,0x07,0x48,0x03,0x33,0x1b,0x1a,0x06,0x2b,
-0x04,0xd9,0x06,0x4b,0x00,0x2b,0x01,0xd0,0x00,0xf0,0x5c,0xf8,0x08,0xbc,0x01,0xbc,
-0x00,0x47,0xc0,0x46,0x50,0x13,0x00,0x20,0x50,0x13,0x00,0x20,0x00,0x00,0x00,0x00,
-0x08,0x48,0x09,0x49,0x09,0x1a,0x89,0x10,0x08,0xb5,0xcb,0x0f,0x59,0x18,0x49,0x10,
-0x04,0xd0,0x06,0x4b,0x00,0x2b,0x01,0xd0,0x00,0xf0,0x44,0xf8,0x08,0xbc,0x01,0xbc,
-0x00,0x47,0xc0,0x46,0x50,0x13,0x00,0x20,0x50,0x13,0x00,0x20,0x00,0x00,0x00,0x00,
-0x10,0xb5,0x08,0x4c,0x23,0x78,0x00,0x2b,0x09,0xd1,0xff,0xf7,0xcb,0xff,0x06,0x4b,
+0x07,0x49,0x4f,0xf0,0x00,0x02,0x88,0x42,0xb8,0xbf,0x40,0xf8,0x04,0x2b,0xff,0xf6,
+0xfa,0xaf,0x00,0xf0,0x71,0xf9,0xfe,0xe7,0xb0,0x0f,0x00,0x20,0x14,0x14,0x00,0x20,
+0xbc,0x14,0x00,0x20,0x10,0xb5,0x07,0x4c,0x23,0x78,0x00,0x2b,0x07,0xd1,0x06,0x4b,
0x00,0x2b,0x02,0xd0,0x05,0x48,0xaf,0xf3,0x00,0x80,0x01,0x23,0x23,0x70,0x10,0xbc,
-0x01,0xbc,0x00,0x47,0x54,0x13,0x00,0x20,0x00,0x00,0x00,0x00,0xe0,0x0e,0x00,0x20,
-0x08,0xb5,0x0b,0x4b,0x00,0x2b,0x03,0xd0,0x0a,0x48,0x0b,0x49,0xaf,0xf3,0x00,0x80,
-0x0a,0x48,0x03,0x68,0x00,0x2b,0x04,0xd1,0xff,0xf7,0xc2,0xff,0x08,0xbc,0x01,0xbc,
-0x00,0x47,0x07,0x4b,0x00,0x2b,0xf7,0xd0,0x00,0xf0,0x0c,0xf8,0xf4,0xe7,0xc0,0x46,
-0x00,0x00,0x00,0x00,0xe0,0x0e,0x00,0x20,0x58,0x13,0x00,0x20,0x4c,0x13,0x00,0x20,
-0x00,0x00,0x00,0x00,0x18,0x47,0xc0,0x46,0xd4,0x30,0x9f,0xe5,0x00,0x00,0x53,0xe3,
-0xc8,0x30,0x9f,0x05,0x03,0xd0,0xa0,0xe1,0x00,0x20,0x0f,0xe1,0x0f,0x00,0x12,0xe3,
-0x15,0x00,0x00,0x0a,0xd1,0xf0,0x21,0xe3,0x03,0xd0,0xa0,0xe1,0x01,0xaa,0x4d,0xe2,
-0x0a,0x30,0xa0,0xe1,0xd7,0xf0,0x21,0xe3,0x03,0xd0,0xa0,0xe1,0x01,0x3a,0x43,0xe2,
-0xdb,0xf0,0x21,0xe3,0x03,0xd0,0xa0,0xe1,0x01,0x3a,0x43,0xe2,0xd2,0xf0,0x21,0xe3,
-0x03,0xd0,0xa0,0xe1,0x02,0x3a,0x43,0xe2,0xd3,0xf0,0x21,0xe3,0x03,0xd0,0xa0,0xe1,
-0x02,0x39,0x43,0xe2,0xff,0x30,0xc3,0xe3,0xff,0x3c,0xc3,0xe3,0x04,0x30,0x03,0xe5,
-0x00,0x20,0x53,0xe9,0xc0,0x20,0x82,0xe3,0x02,0xf0,0x21,0xe1,0x01,0xa8,0x43,0xe2,
-0x00,0x10,0xb0,0xe3,0x01,0xb0,0xa0,0xe1,0x01,0x70,0xa0,0xe1,0x5c,0x00,0x9f,0xe5,
-0x5c,0x20,0x9f,0xe5,0x00,0x20,0x52,0xe0,0x01,0x30,0x8f,0xe2,0x13,0xff,0x2f,0xe1,
-0x00,0xf0,0x42,0xfd,0x10,0x4b,0x00,0x2b,0x01,0xd0,0xfe,0x46,0x9f,0x46,0x0f,0x4b,
-0x00,0x2b,0x01,0xd0,0xfe,0x46,0x9f,0x46,0x00,0x20,0x00,0x21,0x04,0x00,0x0d,0x00,
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-0xd1,0xf8,0x00,0xf0,0x8b,0xfc,0x7b,0x46,0x18,0x47,0x00,0x00,0x11,0x00,0x00,0xef,
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-0x0e,0x46,0x15,0x46,0x00,0x21,0x28,0x22,0x00,0xf0,0x0e,0xfd,0x26,0x61,0x65,0x62,
-0x00,0x21,0x84,0x22,0x02,0x48,0x00,0xf0,0x07,0xfd,0x00,0x20,0x70,0xbd,0x00,0xbf,
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-0x01,0x21,0x84,0x22,0x03,0x48,0x00,0xf0,0xf7,0xfc,0x01,0xe0,0x40,0xf2,0x01,0x14,
-0x20,0x46,0x10,0xbd,0x70,0x13,0x00,0x20,0x01,0x39,0xf8,0xb5,0x44,0x0b,0x08,0x44,
-0x45,0x0b,0x66,0x03,0xac,0x42,0x14,0xd8,0x0b,0x4f,0xe3,0x5d,0x6b,0xb9,0x30,0x46,
-0x00,0xf0,0xfc,0xf8,0x38,0xb1,0x00,0x04,0x00,0xf4,0x7f,0x00,0x40,0xea,0x04,0x60,
-0x40,0xf4,0x81,0x70,0xf8,0xbd,0x01,0x23,0xe3,0x55,0x01,0x34,0x06,0xf5,0x00,0x56,
-0xe8,0xe7,0x00,0x20,0xf8,0xbd,0x00,0xbf,0x70,0x13,0x00,0x20,0x2d,0xe9,0xf0,0x4f,
-0x53,0x1e,0x85,0xb0,0x0b,0x44,0x02,0x90,0x0d,0x46,0x4f,0xea,0x51,0x38,0x5b,0x0b,
-0x16,0x46,0x23,0x48,0x01,0x93,0x00,0x21,0x84,0x22,0x00,0xf0,0xbd,0xfc,0x4f,0xea,
-0x48,0x37,0xc5,0xf3,0x0c,0x0c,0x4f,0xf0,0x00,0x09,0x01,0x9b,0x98,0x45,0x32,0xd8,
-0x74,0x19,0xdf,0xf8,0x70,0xb0,0xcd,0xf8,0x0c,0xc0,0x07,0xf5,0x00,0x5a,0x54,0x45,
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-0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0xd8,0x0f,0x00,0x20,0x61,0x00,0x00,0x20,0x35,0x00,0x00,0x20,0x00,0x00,0x00,0x00,
+0x39,0x0d,0x00,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
diff --git a/contrib/loaders/flash/cc26xx/flash.c
b/contrib/loaders/flash/cc26xx/flash.c
index affd029553..12bd331f02 100644
--- a/contrib/loaders/flash/cc26xx/flash.c
+++ b/contrib/loaders/flash/cc26xx/flash.c
@@ -42,7 +42,7 @@ typedef uint32_t (*flash_sector_erase_pntr_t) (uint32_t);
*
******************************************************************************/
static void issue_fsm_command(flash_state_command_t command);
-static void enable_sectors_for_write(void);
+static void enable_sectors_for_write(uint32_t);
static uint32_t scale_cycle_values(uint32_t specified_timing,
uint32_t scale_value);
static void set_write_mode(void);
@@ -80,42 +80,54 @@ uint32_t flash_bank_erase(bool force_precondition)
uint32_t error_return;
uint32_t sector_address;
uint32_t reg_val;
+ uint32_t bank_no;
+ uint32_t top_bank_start_addr = (HWREG(FLASH_BASE +
FLASH_O_FCFG_B1_START) &
+ FLASH_FCFG_B1_START_B1_START_ADDR_M)
+ >> FLASH_FCFG_B1_START_B1_START_ADDR_S;
- /* Enable all sectors for erase. */
- enable_sectors_for_write();
+ for (bank_no = 0; bank_no < flash_bank_count(); bank_no++) {
+ /* Enable all sectors for erase. */
+ enable_sectors_for_write(bank_no);
- /* Clear the Status register. */
- issue_fsm_command(FAPI_CLEAR_STATUS);
+ /* Clear the Status register. */
+ issue_fsm_command(FAPI_CLEAR_STATUS);
- /* Enable erase of all sectors and enable precondition if required. */
- reg_val = HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE);
- HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE;
- HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR1) = 0x00000000;
- HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR2) = 0x00000000;
- if (force_precondition)
- HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) |=
- FLASH_FSM_ST_MACHINE_DO_PRECOND;
- HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE;
+ /* Enable erase of all sectors and enable precondition if
required. */
+ reg_val = HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE);
+ HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE;
+ HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR1) = 0x00000000;
+ HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR2) = 0x00000000;
+ if (force_precondition)
+ HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) |=
+ FLASH_FSM_ST_MACHINE_DO_PRECOND;
+ HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE;
- /* Issue the bank erase command to the FSM. */
- issue_fsm_command(FAPI_ERASE_BANK);
+ // Write address to FADDR register.
+ HWREG(FLASH_BASE + FLASH_O_FADDR) = ADDR_OFFSET + (bank_no *
top_bank_start_addr);
- /* Wait for erase to finish. */
- while (flash_check_fsm_for_ready() == FAPI_STATUS_FSM_BUSY)
- ;
+ /* Issue the bank erase command to the FSM. */
+ issue_fsm_command(FAPI_ERASE_BANK);
- /* Update status. */
- error_return = flash_check_fsm_for_error();
+ /* Wait for erase to finish. */
+ while (flash_check_fsm_for_ready() == FAPI_STATUS_FSM_BUSY)
+ ;
- /* Disable sectors for erase. */
- flash_disable_sectors_for_write();
+ /* Update status. */
+ error_return = flash_check_fsm_for_error();
- /* Set configured precondition mode since it may have been forced on. */
- if (!(reg_val & FLASH_FSM_ST_MACHINE_DO_PRECOND)) {
- HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE;
- HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) &=
- ~FLASH_FSM_ST_MACHINE_DO_PRECOND;
- HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE;
+ /* Disable sectors for erase. */
+ flash_disable_sectors_for_write();
+
+ /* Set configured precondition mode since it may have been
forced on. */
+ if (!(reg_val & FLASH_FSM_ST_MACHINE_DO_PRECOND)) {
+ HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) =
FSM_REG_WRT_ENABLE;
+ HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) &=
+ ~FLASH_FSM_ST_MACHINE_DO_PRECOND;
+ HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) =
FSM_REG_WRT_DISABLE;
+ }
+
+ if (error_return != FAPI_STATUS_SUCCESS)
+ break;
}
/* Program security data to default values in the customer
configuration */
@@ -139,18 +151,91 @@ uint32_t flash_bank_erase(bool force_precondition)
******************************************************************************/
uint32_t flash_program(uint8_t *data_buffer, uint32_t address, uint32_t count)
{
+ uint32_t start_index;
+ uint32_t stop_index;
+ uint32_t index;
+ uint8_t bank_width;
+ uint8_t no_of_bytes;
+ fwp_write_byte *p_write_byte;
uint32_t error_return;
- flash_prg_pntr_t func_pntr;
+ uint32_t bank_no;
+ uint32_t top_bank_start_addr = (HWREG(FLASH_BASE +
FLASH_O_FCFG_B1_START) &
+ FLASH_FCFG_B1_START_B1_START_ADDR_M)
+ >> FLASH_FCFG_B1_START_B1_START_ADDR_S;
+
+ bank_no = 0;
+ /* FIXME: Assumes only two banks */
+ if (address >= top_bank_start_addr)
+ bank_no = 1;
+
+ // Enable sectors for programming in target bank.
+ enable_sectors_for_write(bank_no);
+ p_write_byte = FWPWRITE_BYTE_ADDRESS;
+
+ // Check the arguments.
+ if ((address + count) > (FLASHMEM_BASE + flash_size_get())) {
+ // Invalid arguments. Exit function!
+ flash_disable_sectors_for_write();
+ return FAPI_STATUS_INCORRECT_DATABUFFER_LENGTH;
+ }
- /* Call ROM function */
- func_pntr = (uint32_t (*)(uint8_t *, uint32_t, uint32_t))
- (ROM_API_FLASH_TABLE[6]);
- error_return = func_pntr(data_buffer, address, count);
+ // Set the status to indicate success.
+ error_return = FAPI_STATUS_SUCCESS;
- /* Enable standby because ROM function might have disabled it */
- HWREGBITW(FLASH_BASE + FLASH_O_CFG, FLASH_CFG_DIS_STANDBY_BITN) = 0;
+ // Find flash bank width in number of bytes.
+ bank_width = flash_bank_width();
- /* Return status of operation. */
+ // Loop over the bytes to be programmed.
+ while (count) {
+ // Setup the start position within the write data registers.
+ start_index = address & (uint32_t)(bank_width - 1);
+
+ // Setup number of bytes to program.
+ no_of_bytes = bank_width - start_index;
+ if (no_of_bytes > count)
+ no_of_bytes = count;
+
+ // Clear the Status register.
+ issue_fsm_command(FAPI_CLEAR_STATUS);
+
+ // Write address to FADDR register.
+ HWREG(FLASH_BASE + FLASH_O_FADDR) = address + ADDR_OFFSET;
+
+ // Setup the stop position within the write data registers.
+ stop_index = start_index + (uint32_t)(no_of_bytes - 1);
+
+ // Write each byte to the FWPWrite registers.
+ for (index = start_index; index <= stop_index; index++)
+ p_write_byte[index] = *(data_buffer++);
+
+ // Issue the Program command to the FSM.
+ issue_fsm_command(FAPI_PROGRAM_DATA);
+
+ // Wait until the word has been programmed.
+ while (flash_check_fsm_for_ready() == FAPI_STATUS_FSM_BUSY)
+ ;
+
+ // Exit if an access violation occurred.
+ error_return = flash_check_fsm_for_error();
+ if (error_return != FAPI_STATUS_SUCCESS)
+ break;
+
+ // Prepare for next data burst.
+ count -= ((stop_index - start_index) + 1);
+ address += ((stop_index - start_index) + 1);
+ // Check if next data burst require change of target bank
+ if (bank_no == 0 && address >= top_bank_start_addr) {
+ // Change target bank.
+ flash_disable_sectors_for_write();
+ bank_no = 1;
+ enable_sectors_for_write(bank_no);
+ }
+ }
+
+ // Disable sectors for programming.
+ flash_disable_sectors_for_write();
+
+ // Return status of operation.
return error_return;
}
@@ -161,23 +246,34 @@ uint32_t flash_program(uint8_t *data_buffer, uint32_t
address, uint32_t count)
******************************************************************************/
void flash_disable_sectors_for_write(void)
{
+ uint32_t bank_no;
+
/* Configure flash back to read mode */
set_read_mode();
- /* Disable Level 1 Protection. */
- HWREG(FLASH_BASE + FLASH_O_FBPROT) = FLASH_FBPROT_PROTL1DIS;
+ for (bank_no = 0; bank_no < flash_bank_count(); bank_no++) {
- /* Disable all sectors for erase and programming. */
- HWREG(FLASH_BASE + FLASH_O_FBSE) = 0x0000;
+ /* Select flash bank. */
+ HWREG(FLASH_BASE + FLASH_O_FMAC) = bank_no;
- /* Enable Level 1 Protection. */
- HWREG(FLASH_BASE + FLASH_O_FBPROT) = 0;
+ /* Disable Level 1 Protection. */
+ HWREG(FLASH_BASE + FLASH_O_FBPROT) = FLASH_FBPROT_PROTL1DIS;
- /* Protect sectors from sector erase. */
- HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE;
- HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR1) = 0xFFFFFFFF;
- HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR2) = 0xFFFFFFFF;
- HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE;
+ /* Disable all sectors for erase and programming. */
+ HWREG(FLASH_BASE + FLASH_O_FBSE) = 0x0000;
+
+ /* Enable Level 1 Protection. */
+ HWREG(FLASH_BASE + FLASH_O_FBPROT) = 0;
+
+ /* Protect sectors from sector erase. */
+ HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE;
+ HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR1) = 0xFFFFFFFF;
+ HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR2) = 0xFFFFFFFF;
+ HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE;
+ }
+
+ // Select bank 0
+ HWREG(FLASH_BASE + FLASH_O_FMAC) = 0x0;
}
/******************************************************************************
@@ -214,7 +310,7 @@ static void issue_fsm_command(flash_state_command_t command)
* the FLASH_O_FSM_SECTOR1 register.
*
******************************************************************************/
-static void enable_sectors_for_write(void)
+static void enable_sectors_for_write(uint32_t bank_no)
{
/* Trim flash module for program/erase operation. */
trim_for_write();
@@ -223,7 +319,7 @@ static void enable_sectors_for_write(void)
set_write_mode();
/* Select flash bank. */
- HWREG(FLASH_BASE + FLASH_O_FMAC) = 0x00;
+ HWREG(FLASH_BASE + FLASH_O_FMAC) = bank_no;
/* Disable Level 1 Protection. */
HWREG(FLASH_BASE + FLASH_O_FBPROT) = FLASH_FBPROT_PROTL1DIS;
diff --git a/contrib/loaders/flash/cc26xx/flash.h
b/contrib/loaders/flash/cc26xx/flash.h
index 07acf26f2a..2fb698cba7 100644
--- a/contrib/loaders/flash/cc26xx/flash.h
+++ b/contrib/loaders/flash/cc26xx/flash.h
@@ -26,7 +26,7 @@ extern "C"
#define ROM_VERSION (ROM_API_TABLE[0])
#define ROM_API_FLASH_TABLE ((uint32_t *) (ROM_API_TABLE[10]))
-#if defined(DEVICE_CC26X2)
+#if defined(DEVICE_CC26X2) || defined(DEVICE_CC26X2X7)
/* Agama (CC26x2) specific definitions */
@@ -246,6 +246,46 @@ static inline uint32_t flash_check_fsm_for_ready(void)
return FAPI_STATUS_FSM_READY;
}
+/******************************************************************************
+ *
+ * Get the number of banks
+ *
+ * This function returns the number of bank of the flash.
+ *
+ * Returns the number of banks
+ *
+
******************************************************************************/
+static inline uint32_t flash_bank_count(void)
+{
+ uint32_t bank_count;
+
+ bank_count = (HWREG(FLASH_BASE + FLASH_O_FCFG_BANK) &
+ FLASH_FCFG_BANK_MAIN_NUM_BANK_M) >>
+ FLASH_FCFG_BANK_MAIN_NUM_BANK_S;
+
+ return bank_count;
+}
+
+/******************************************************************************
+ *
+ * Get the size of the bank.
+ *
+ * This function returns the size of the main bank in number of bytes.
+ *
+ * Returns the flash size in number of bytes.
+ *
+
******************************************************************************/
+static inline uint8_t flash_bank_width(void)
+{
+ uint8_t bank_width;
+
+ bank_width = (uint8_t)(((HWREG(FLASH_BASE + FLASH_O_FCFG_BANK) &
+ FLASH_FCFG_BANK_MAIN_BANK_WIDTH_M) >>
+ FLASH_FCFG_BANK_MAIN_BANK_WIDTH_S) >> 3);
+
+ return bank_width;
+}
+
/******************************************************************************
*
* Erase a flash sector.
diff --git a/contrib/loaders/flash/cc26xx/hw_regs.h
b/contrib/loaders/flash/cc26xx/hw_regs.h
index 78c81be242..7d577654c3 100644
--- a/contrib/loaders/flash/cc26xx/hw_regs.h
+++ b/contrib/loaders/flash/cc26xx/hw_regs.h
@@ -116,6 +116,10 @@
/* FMC Sequential Pump Information */
#define FLASH_O_FSEQPMP 0x000020A8
+#define FLASH_O_FADDR 0x00002110
+
+#define FLASH_O_FWPWRITE0 0x00002120
+
/* FMC FSM Command */
#define FLASH_O_FSM_CMD 0x0000220C
@@ -179,9 +183,14 @@
/* FMC FSM Sector Erased 2 */
#define FLASH_O_FSM_SECTOR2 0x000022C4
+#define FLASH_O_FCFG_BANK 0x00002400
+
/* FMC Flash Bank 0 Starting Address */
#define FLASH_O_FCFG_B0_START 0x00002410
+/* FMC Flash Bank 1 Starting Address */
+#define FLASH_O_FCFG_B1_START 0x00002414
+
/* FMC Flash Bank 0 Sector Size 0 */
#define FLASH_O_FCFG_B0_SSIZE0 0x00002430
@@ -1337,7 +1346,7 @@
******************************************************************************/
/* Power Management Control */
-#if defined(DEVICE_CC26X2)
+#if defined(DEVICE_CC26X2) || defined(DEVICE_CC26X2X7)
/* Agama (CC26x2) specific definition */
#define AON_PMCTL_O_PWRCTL 0x00000010
#elif defined(DEVICE_CC26X0)
@@ -1353,4 +1362,16 @@
* 1: DCDC and GLDO are bypassed and an external regulator supplies VDDR */
#define AON_PMCTL_PWRCTL_EXT_REG_MODE 0x00000002
+/* Field: [3:0] MAIN_NUM_BANK */
+#define FLASH_FCFG_BANK_MAIN_NUM_BANK_M 0x0000000F
+#define FLASH_FCFG_BANK_MAIN_NUM_BANK_S 0
+
+/* Field: [23:0] B1_START_ADDR */
+#define FLASH_FCFG_B1_START_B1_START_ADDR_M 0x00FFFFFF
+#define FLASH_FCFG_B1_START_B1_START_ADDR_S 0
+
+/* Field: [15:4] MAIN_BANK_WIDTH */
+#define FLASH_FCFG_BANK_MAIN_BANK_WIDTH_M 0x0000FFF0
+#define FLASH_FCFG_BANK_MAIN_BANK_WIDTH_S 4
+
#endif /* #ifndef OPENOCD_LOADERS_FLASH_CC26XX_HW_REGS_H */
--
