This is an automated email from Gerrit.
"zapb <d...@zapb.de>" just uploaded a new patch set to Gerrit, which you can
find at https://review.openocd.org/c/openocd/+/8337
-- gerrit
commit a5a998ef88f3b846c5c5f84f90428dc85f02bc3f
Author: Marc Schink <d...@zapb.de>
Date: Fri Jun 14 16:28:38 2024 +0200
tcl: Replace 'gdb_' prefix with 'gdb' command group
Change-Id: I0490b4c112c1a922bf77a4b37df2a630a8f6cea1
Signed-off-by: Marc Schink <d...@zapb.de>
diff --git a/tcl/board/actux3.cfg b/tcl/board/actux3.cfg
index edb529c889..7c2ce06773 100644
--- a/tcl/board/actux3.cfg
+++ b/tcl/board/actux3.cfg
@@ -50,7 +50,7 @@ reset init
# setup to debug u-boot in flash
proc uboot_debug {} {
- gdb_breakpoint_override hard
+ gdb breakpoint_override hard
xscale vector_catch 0xFF
xscale vector_table low 1 0xe59ff018
diff --git a/tcl/board/mini2440.cfg b/tcl/board/mini2440.cfg
index 85d9a35b9a..5642cb1ab8 100644
--- a/tcl/board/mini2440.cfg
+++ b/tcl/board/mini2440.cfg
@@ -128,7 +128,7 @@ reset_config trst_and_srst
# GDB Setup
#-------------------------------------------------------------------------
- gdb_breakpoint_override hard
+ gdb breakpoint_override hard
#------------------------------------------------
# ARM SPECIFIC
diff --git a/tcl/board/mini6410.cfg b/tcl/board/mini6410.cfg
index 18f9e8d25a..276e7180ea 100644
--- a/tcl/board/mini6410.cfg
+++ b/tcl/board/mini6410.cfg
@@ -95,7 +95,7 @@ adapter srst delay 100
jtag_ntrst_delay 100
reset_config trst_and_srst
-gdb_breakpoint_override hard
+gdb breakpoint_override hard
targets
nand device $_CHIPNAME.flash s3c6400 $_CHIPNAME.cpu
diff --git a/tcl/board/or1k_generic.cfg b/tcl/board/or1k_generic.cfg
index 915a0de249..b6cf3a0978 100644
--- a/tcl/board/or1k_generic.cfg
+++ b/tcl/board/or1k_generic.cfg
@@ -22,7 +22,7 @@ poll_period 1
adapter speed 3000
# Enable the target description feature
-gdb_target_description enable
+gdb target_description enable
# Add a new register in the cpu register list. This register will be
# included in the generated target descriptor file.
diff --git a/tcl/interface/vdebug.cfg b/tcl/interface/vdebug.cfg
index 7350bb9a91..116ac8a758 100644
--- a/tcl/interface/vdebug.cfg
+++ b/tcl/interface/vdebug.cfg
@@ -22,7 +22,7 @@ vdebug server $_VDEBUGHOST:$_VDEBUGPORT
# example config listen on all interfaces, disable tcl/telnet server
bindto 0.0.0.0
-#gdb_port 3333
+#gdb port 3333
#telnet_port disabled
tcl_port disabled
diff --git a/tcl/target/esi32xx.cfg b/tcl/target/esi32xx.cfg
index a8b0823dac..d29c636cfa 100644
--- a/tcl/target/esi32xx.cfg
+++ b/tcl/target/esi32xx.cfg
@@ -35,4 +35,4 @@ reset_config none
# The default linker scripts provided by the eSi-RISC toolchain do not
# specify attributes on memory regions, which results in incorrect
# application of software breakpoints by GDB.
-gdb_breakpoint_override hard
+gdb breakpoint_override hard
diff --git a/tcl/target/esp_common.cfg b/tcl/target/esp_common.cfg
index ac8cd6a198..e9a188f9f6 100644
--- a/tcl/target/esp_common.cfg
+++ b/tcl/target/esp_common.cfg
@@ -181,7 +181,7 @@ proc configure_esp_xtensa_default_settings { } {
$_TARGETNAME_0 xtensa smpbreak BreakIn BreakOut
}
- gdb_breakpoint_override hard
+ gdb breakpoint_override hard
if { [info exists _FLASH_VOLTAGE] } {
$_TARGETNAME_0 $_CHIPNAME flashbootstrap $_FLASH_VOLTAGE
diff --git a/tcl/target/omap4430.cfg b/tcl/target/omap4430.cfg
index a448550f67..4bc7fe1bf7 100644
--- a/tcl/target/omap4430.cfg
+++ b/tcl/target/omap4430.cfg
@@ -128,4 +128,4 @@ $_CHIPNAME.m30 configure -event reset-assert { }
$_CHIPNAME.m31 configure -event reset-assert { }
# Soft breakpoints don't currently work due to broken cache handling
-gdb_breakpoint_override hard
+gdb breakpoint_override hard
diff --git a/tcl/target/omap4460.cfg b/tcl/target/omap4460.cfg
index bbc824b2af..85ba96c51f 100644
--- a/tcl/target/omap4460.cfg
+++ b/tcl/target/omap4460.cfg
@@ -128,4 +128,4 @@ $_CHIPNAME.m30 configure -event reset-assert { }
$_CHIPNAME.m31 configure -event reset-assert { }
# Soft breakpoints don't currently work due to broken cache handling
-gdb_breakpoint_override hard
+gdb breakpoint_override hard
diff --git a/tcl/target/omapl138.cfg b/tcl/target/omapl138.cfg
index 2d670b98a3..78c456d5c0 100644
--- a/tcl/target/omapl138.cfg
+++ b/tcl/target/omapl138.cfg
@@ -64,5 +64,5 @@ arm7_9 dcc_downloads enable
etm config $_TARGETNAME 16 normal full etb
etb config $_TARGETNAME $_CHIPNAME.etb
-gdb_breakpoint_override hard
+gdb breakpoint_override hard
arm7_9 dbgrq enable
diff --git a/tcl/target/rp2040.cfg b/tcl/target/rp2040.cfg
index de76b4e29c..5e78c69310 100644
--- a/tcl/target/rp2040.cfg
+++ b/tcl/target/rp2040.cfg
@@ -96,7 +96,7 @@ if { $_USE_CORE == 1 } {
set _FLASH_TARGET $_TARGETNAME_0
}
# Backup the work area. The flash probe runs an algorithm on the target CPU.
-# The flash is probed during gdb connect if gdb_memory_map is enabled (by
default).
+# The flash is probed during gdb connect if gdb memory_map is enabled (by
default).
$_FLASH_TARGET configure -work-area-phys 0x20010000 -work-area-size
$_WORKAREASIZE -work-area-backup 1
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME rp2040_flash 0x10000000 0 0 0 $_FLASH_TARGET
diff --git a/tcl/target/u8500.cfg b/tcl/target/u8500.cfg
index 417fdd18f2..932ef8c20d 100644
--- a/tcl/target/u8500.cfg
+++ b/tcl/target/u8500.cfg
@@ -144,7 +144,7 @@ proc enable_apetap {} {
tcl_port 5555
telnet_port 4444
-gdb_port 3333
+gdb port 3333
if { [info exists CHIPNAME] } {
global _CHIPNAME
@@ -319,7 +319,7 @@ global _MAXSPEED
adapter speed $_MAXSPEED
-gdb_breakpoint_override hard
+gdb breakpoint_override hard
set mem inaccessible-by-default-off
jtag_ntrst_delay 100
diff --git a/tcl/target/xtensa.cfg b/tcl/target/xtensa.cfg
index 561131d842..c277673e47 100644
--- a/tcl/target/xtensa.cfg
+++ b/tcl/target/xtensa.cfg
@@ -67,4 +67,4 @@ if { $_XTENSA_NUM_CORES == 1 } {
$_TARGETNAME configure -event reset-assert-post { soft_reset_halt }
}
-gdb_report_register_access_error enable
+gdb report_register_access_error enable
--
