[PATCH]: b5727961ef target: add NXP imx93 and EVK board support

[gerrit]

This is an automated email from Gerrit.

"Peter pan <peter.pa...@gmail.com>" just uploaded a new patch set to Gerrit, 
which you can find at https://review.openocd.org/c/openocd/+/8353

-- gerrit

commit b5727961ef0619018193e44da8f9d668785fe29b
Author: Jiafei Pan <jiafei....@nxp.com>
Date:   Tue Jun 18 12:16:42 2024 +0800

    target: add NXP imx93 and EVK board support
    
    Have verified with JLink:
    openocd -f interface/jlink.cfg -f board/nxp_imx93-evk.cfg
    
    Change-Id: I9363b67cf56bc8615b06d7b64b75e7fe398e1c45
    Signed-off-by: Jiafei Pan <jiafei....@nxp.com>

diff --git a/tcl/board/nxp_imx93-evk.cfg b/tcl/board/nxp_imx93-evk.cfg
new file mode 100644
index 0000000000..7dfbf77ad0
--- /dev/null
+++ b/tcl/board/nxp_imx93-evk.cfg
@@ -0,0 +1,25 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# configuration file for NXP i.MX93 EVK
+#
+
+# only JTAG supported
+transport select jtag
+
+# set a safe JTAG clock speed, can be overridden
+adapter speed 1000
+
+# default JTAG configuration has only SRST and no TRST
+reset_config srst_only srst_push_pull
+
+# delay after SRST goes inactive
+adapter srst delay 70
+
+
+# board has an i.MX93 with 2 Cortex-A55 cores
+set CHIPNAME imx93
+set CHIPCORES 2
+
+# source SoC configuration
+source [find target/imx93.cfg]
diff --git a/tcl/target/imx93.cfg b/tcl/target/imx93.cfg
new file mode 100644
index 0000000000..b5484f9463
--- /dev/null
+++ b/tcl/target/imx93.cfg
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# configuration file for NXP i.MX93 family of SoCs
+#
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
+   set  _CHIPNAME imx93
+}
+
+if { [info exists CHIPCORES] } {
+    set _cores $CHIPCORES
+} else {
+    set _cores 1
+}
+
+# CoreSight Debug Access Port
+if { [info exists DAP_TAPID] } {
+        set _DAP_TAPID $DAP_TAPID
+} else {
+        set _DAP_TAPID 0x0892801d
+}
+
+# the DAP tap
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \
+        -expected-id $_DAP_TAPID
+
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.a55
+set _CTINAME $_CHIPNAME.cti
+
+set DBGBASE {0x40810000 0x40910000}
+set CTIBASE {0x40820000 0x40920000}
+
+for { set _core 0 } { $_core < $_cores } { incr _core } {
+
+    cti create $_CTINAME.$_core -dap $_CHIPNAME.dap -ap-num 1 \
+        -baseaddr [lindex $CTIBASE $_core]
+
+    set _command "target create $_TARGETNAME.$_core aarch64 -dap 
$_CHIPNAME.dap \
+        -dbgbase [lindex $DBGBASE $_core] -cti $_CTINAME.$_core -coreid $_core"
+
+    eval $_command
+}
+
+# declare the auxiliary Cortex-M33 core on AP #4
+target create ${_CHIPNAME}.m33 cortex_m -dap ${_CHIPNAME}.dap -ap-num 3
+
+# AHB-AP for direct access to soc bus
+target create ${_CHIPNAME}.ahb mem_ap -dap ${_CHIPNAME}.dap -ap-num 0
+
+# default target is A55 core 0
+targets $_TARGETNAME.1

--