This is an automated email from Gerrit.
"Antonio Borneo <borneo.anto...@gmail.com>" just uploaded a new patch set to
Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8409
-- gerrit
commit 007f9b1a59343e1117227dd48f263e6814f70187
Author: Antonio Borneo <borneo.anto...@gmail.com>
Date: Sun Jul 21 13:04:36 2024 +0200
tcl: fix minor typos and repeated words
Detected with checkpatch.
Change-Id: Id306928496cf70bbe7ff065bf726bc7dceadce26
Signed-off-by: Antonio Borneo <borneo.anto...@gmail.com>
diff --git a/tcl/board/at91sam9g20-ek.cfg b/tcl/board/at91sam9g20-ek.cfg
index 4740471c89..22a38a7089 100644
--- a/tcl/board/at91sam9g20-ek.cfg
+++ b/tcl/board/at91sam9g20-ek.cfg
@@ -43,7 +43,7 @@ proc read_register {register} {
proc at91sam9g20_reset_start { } {
- # Make sure that the the jtag is running slow, since there are a number
of different ways the board
+ # Make sure that the jtag is running slow, since there are a number of
different ways the board
# can be configured coming into this state that can cause communication
problems with the jtag
# adapter. Also since this call can be made following a "reset init"
where fast memory accesses
# are enabled, need to temporarily shut this down so that the RSTC_MR
register can be written at slower
@@ -202,7 +202,7 @@ proc at91sam9g20_reset_init { } {
mww 0xffffea00 0x3
mww 0x20000000 0
- # Signal normal mode using the SDRAMC_MR register and follow with a
zero value write the the starting
+ # Signal normal mode using the SDRAMC_MR register and follow with a
zero value write the starting
# memory location for the SDRAM.
mww 0xffffea00 0x0
diff --git a/tcl/board/netgear-wg102.cfg b/tcl/board/netgear-wg102.cfg
index 15f9c118af..0a7dad5ab2 100644
--- a/tcl/board/netgear-wg102.cfg
+++ b/tcl/board/netgear-wg102.cfg
@@ -27,7 +27,7 @@ $_TARGETNAME configure -event reset-init {
# 0x00003800 - 0x07 << FLASHCTL_WST2_S
# FLASHCTL_AC_8M 0x00060000 - Size of flash
# FLASHCTL_E 0x00080000 - Flash bank enable (added)
- # FLASHCTL_WP 0x04000000 - write protect. If used, CFI mode wont
work!!
+ # FLASHCTL_WP 0x04000000 - write protect. If used, CFI mode won't
work!!
# FLASHCTL_MWx16 0x10000000 - 16bit mode. Do not use it!!
# FLASHCTL_MWx8 0x00000000 - 8bit mode.
mww 0xb8400000 0x000d3ce1
diff --git a/tcl/target/allwinner_v3s.cfg b/tcl/target/allwinner_v3s.cfg
index 437bd956df..6c3435ed74 100644
--- a/tcl/target/allwinner_v3s.cfg
+++ b/tcl/target/allwinner_v3s.cfg
@@ -28,7 +28,7 @@
# UART2_TX PB0 Per default disabled
# UART2_RX PB1 Per default disabled
#
-# JTAG is enabled by default after power on on listed JTAG_* pins. So far the
+# JTAG is enabled by default after power-on on listed JTAG_* pins. So far the
# boot sequence is:
# Time Action
# 0000ms Power ON
diff --git a/tcl/target/ampere_emag.cfg b/tcl/target/ampere_emag.cfg
index 0b0bd9e88d..fd68fcd482 100644
--- a/tcl/target/ampere_emag.cfg
+++ b/tcl/target/ampere_emag.cfg
@@ -8,7 +8,7 @@
#
# Configure defaults for target
-# Can be overriden in board configuration file
+# Can be overridden in board configuration file
#
if { [info exists CHIPNAME] } {
diff --git a/tcl/target/icepick.cfg b/tcl/target/icepick.cfg
index 5509532111..e5d5706f02 100644
--- a/tcl/target/icepick.cfg
+++ b/tcl/target/icepick.cfg
@@ -6,7 +6,7 @@
#
# Utilities for TI ICEpick-C/D used in most TI SoCs
-# Details about the ICEPick are available in the the TRM for each SoC
+# Details about the ICEPick are available in the TRM for each SoC
# and http://processors.wiki.ti.com/index.php/ICEPICK
# create "constants"
--
