[PATCH]: 6aef2148db tcl/target/rp2040: add flash size override and reset init event

[gerrit]

This is an automated email from Gerrit.

"Tomas Vanek <van...@fbl.cz>" just uploaded a new patch set to Gerrit, which 
you can find at https://review.openocd.org/c/openocd/+/8461

-- gerrit

commit 6aef2148db00b0568234fcbae02a7ae788008988
Author: Tomas Vanek <van...@fbl.cz>
Date:   Sat Aug 17 16:21:06 2024 +0200

    tcl/target/rp2040: add flash size override and reset init event
    
    Allow flash size override and supress flash size detection
    by setting FLASHSIZE Tcl variable.
    
    reset-init event calls 'connect XIP' ROM API function to make
    flash content accessible at the XIP mapping memory area.
    
    Ported from rp2350.cfg
    
    Change-Id: I9b352b1ef6d4c6d4b78a6b61e900ce01355c8eff
    Signed-off-by: Tomas Vanek <van...@fbl.cz>

diff --git a/tcl/target/rp2040.cfg b/tcl/target/rp2040.cfg
index 5fae390b41..f64d4322b1 100644
--- a/tcl/target/rp2040.cfg
+++ b/tcl/target/rp2040.cfg
@@ -20,6 +20,14 @@ if { [info exists WORKAREASIZE] } {
        set _WORKAREASIZE 0x10000
 }
 
+# Nonzero FLASHSIZE supresses QSPI flash size detection
+if { [info exists FLASHSIZE] } {
+       set _FLASHSIZE $FLASHSIZE
+} else {
+       # Detect QSPI flash size based on flash ID or SFDP
+       set _FLASHSIZE 0
+}
+
 if { [info exists CPUTAPID] } {
        set _CPUTAPID $CPUTAPID
 } else {
@@ -74,6 +82,10 @@ if { $_USE_CORE != 1 } {
        target create $_TARGETNAME_0 cortex_m -dap $_CHIPNAME.dap0 -coreid 0
        # srst does not exist; use SYSRESETREQ to perform a soft reset
        $_TARGETNAME_0 cortex_m reset_config sysresetreq
+
+       # After a rescue reset and fi BOOTSEL is halted connect the flash to 
enable
+       # reads from the XIP cached mapping area
+       $_TARGETNAME_0 configure -event reset-init { rp2xxx rom_api_call 0 CX }
 }
 
 # core 1
@@ -95,11 +107,11 @@ if { $_USE_CORE == 1 } {
 } else {
        set _FLASH_TARGET $_TARGETNAME_0
 }
-# Backup the work area. The flash probe runs an algorithm on the target CPU.
-# The flash is probed during gdb connect if gdb memory_map is enabled (by 
default).
-$_FLASH_TARGET configure -work-area-phys 0x20010000 -work-area-size 
$_WORKAREASIZE -work-area-backup 1
+# QSPI flash size detection during gdb connect requires to back-up RAM
+set _WKA_BACKUP [expr { $_FLASHSIZE == 0 }]
+$_FLASH_TARGET configure -work-area-phys 0x20010000 -work-area-size 
$_WORKAREASIZE -work-area-backup $_WKA_BACKUP
 set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME rp2xxx 0x10000000 0 0 0 $_FLASH_TARGET
+flash bank $_FLASHNAME rp2xxx 0x10000000 $_FLASHSIZE 0 0 $_FLASH_TARGET
 
 if { $_BOTH_CORES } {
        # Alias to ensure gdb connecting to core 1 gets the correct memory map

--