This is an automated email from Gerrit.
"Antonio Borneo <borneo.anto...@gmail.com>" just uploaded a new patch set to
Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8497
-- gerrit
commit 3ddd4f8dd01fb0807e2c14320dac5f732f784b22
Author: Antonio Borneo <borneo.anto...@gmail.com>
Date: Mon Sep 16 13:45:19 2024 +0200
OpenOCD: fix code indentation
Fix checkpatch errors
ERROR:SUSPECT_CODE_INDENT: suspect code indent for
conditional statements
Change-Id: I94d4fa5720c25dd2fb0334a824cd9026babcce4e
Signed-off-by: Antonio Borneo <borneo.anto...@gmail.com>
diff --git a/src/flash/nor/fespi.c b/src/flash/nor/fespi.c
index 9191764a96..b945266661 100644
--- a/src/flash/nor/fespi.c
+++ b/src/flash/nor/fespi.c
@@ -751,9 +751,9 @@ static int fespi_probe(struct flash_bank *bank)
target_device->name, bank->base);
} else {
- LOG_DEBUG("Assuming FESPI as specified at address " TARGET_ADDR_FMT
- " with ctrl at " TARGET_ADDR_FMT,
fespi_info->ctrl_base,
- bank->base);
+ LOG_DEBUG("Assuming FESPI as specified at address "
TARGET_ADDR_FMT
+ " with ctrl at " TARGET_ADDR_FMT,
fespi_info->ctrl_base,
+ bank->base);
}
/* read and decode flash ID; returns in SW mode */
diff --git a/src/flash/nor/kinetis_ke.c b/src/flash/nor/kinetis_ke.c
index c069f3ac89..4cd4597c3a 100644
--- a/src/flash/nor/kinetis_ke.c
+++ b/src/flash/nor/kinetis_ke.c
@@ -1005,7 +1005,7 @@ static int kinetis_ke_write(struct flash_bank *bank,
const uint8_t *buffer,
result = kinetis_ke_stop_watchdog(bank->target);
if (result != ERROR_OK)
- return result;
+ return result;
result = kinetis_ke_prepare_flash(bank);
if (result != ERROR_OK)
diff --git a/src/flash/nor/niietcm4.c b/src/flash/nor/niietcm4.c
index 0c36e2c96d..aaf0726550 100644
--- a/src/flash/nor/niietcm4.c
+++ b/src/flash/nor/niietcm4.c
@@ -311,7 +311,7 @@ static int niietcm4_uflash_page_erase(struct flash_bank
*bank, int page_num, int
/* status check */
retval = niietcm4_uopstatus_check(bank);
if (retval != ERROR_OK)
- return retval;
+ return retval;
return retval;
}
@@ -394,7 +394,7 @@ COMMAND_HANDLER(niietcm4_handle_uflash_read_byte_command)
uint32_t uflash_data;
if (strcmp("info", CMD_ARGV[0]) == 0)
- uflash_cmd = UFMC_MAGIC_KEY | UFMC_READ_IFB;
+ uflash_cmd = UFMC_MAGIC_KEY | UFMC_READ_IFB;
else if (strcmp("main", CMD_ARGV[0]) == 0)
uflash_cmd = UFMC_MAGIC_KEY | UFMC_READ;
else
@@ -539,7 +539,7 @@ COMMAND_HANDLER(niietcm4_handle_uflash_erase_command)
int mem_type;
if (strcmp("info", CMD_ARGV[0]) == 0)
- mem_type = 1;
+ mem_type = 1;
else if (strcmp("main", CMD_ARGV[0]) == 0)
mem_type = 0;
else
diff --git a/src/flash/nor/psoc4.c b/src/flash/nor/psoc4.c
index 1064fa93d3..72cf0ee05b 100644
--- a/src/flash/nor/psoc4.c
+++ b/src/flash/nor/psoc4.c
@@ -384,15 +384,15 @@ static int psoc4_get_silicon_id(struct flash_bank *bank,
uint32_t *silicon_id, u
* bit 7..0 family ID (lowest 8 bits)
*/
if (silicon_id)
- *silicon_id = ((part0 & 0x0000ffff) << 16)
- | ((part0 & 0x00ff0000) >> 8)
- | (part1 & 0x000000ff);
+ *silicon_id = ((part0 & 0x0000ffff) << 16)
+ | ((part0 & 0x00ff0000) >> 8)
+ | (part1 & 0x000000ff);
if (family_id)
- *family_id = part1 & 0x0fff;
+ *family_id = part1 & 0x0fff;
if (protection)
- *protection = (part1 >> 12) & 0x0f;
+ *protection = (part1 >> 12) & 0x0f;
return ERROR_OK;
}
diff --git a/src/helper/log.c b/src/helper/log.c
index 471069adee..301c82f566 100644
--- a/src/helper/log.c
+++ b/src/helper/log.c
@@ -272,10 +272,10 @@ void log_init(void)
if (debug_env) {
int value;
int retval = parse_int(debug_env, &value);
- if (retval == ERROR_OK &&
- debug_level >= LOG_LVL_SILENT &&
- debug_level <= LOG_LVL_DEBUG_IO)
- debug_level = value;
+ if (retval == ERROR_OK
+ && debug_level >= LOG_LVL_SILENT
+ && debug_level <= LOG_LVL_DEBUG_IO)
+ debug_level = value;
}
if (!log_output)
diff --git a/src/rtos/hwthread.c b/src/rtos/hwthread.c
index bf927e71a1..2228c3a776 100644
--- a/src/rtos/hwthread.c
+++ b/src/rtos/hwthread.c
@@ -154,9 +154,8 @@ static int hwthread_update_threads(struct rtos *rtos)
if (curr->debug_reason ==
DBG_REASON_SINGLESTEP) {
current_reason = curr->debug_reason;
current_thread = tid;
- } else
- /* multiple breakpoints, prefer gdbs' threadid
*/
- if (curr->debug_reason ==
DBG_REASON_BREAKPOINT) {
+ } else if (curr->debug_reason ==
DBG_REASON_BREAKPOINT) {
+ /* multiple breakpoints, prefer gdbs'
threadid */
if (tid == rtos->current_threadid)
current_thread = tid;
}
@@ -176,8 +175,7 @@ static int hwthread_update_threads(struct rtos *rtos)
curr->debug_reason ==
DBG_REASON_BREAKPOINT) {
current_reason = curr->debug_reason;
current_thread = tid;
- } else
- if (curr->debug_reason == DBG_REASON_DBGRQ) {
+ } else if (curr->debug_reason ==
DBG_REASON_DBGRQ) {
if (tid == rtos->current_threadid)
current_thread = tid;
}
diff --git a/src/rtos/linux.c b/src/rtos/linux.c
index 7517ec7a9a..5467988f3e 100644
--- a/src/rtos/linux.c
+++ b/src/rtos/linux.c
@@ -624,7 +624,7 @@ static struct threads *liste_add_task(struct threads
*task_list, struct threads
{
t->next = NULL;
- if (!*last)
+ if (!*last) {
if (!task_list) {
task_list = t;
return task_list;
@@ -637,7 +637,8 @@ static struct threads *liste_add_task(struct threads
*task_list, struct threads
temp->next = t;
*last = t;
return task_list;
- } else {
+ }
+ } else {
(*last)->next = t;
*last = t;
return task_list;
diff --git a/src/target/aarch64.c b/src/target/aarch64.c
index 6a70b2ddf8..b78fb5b832 100644
--- a/src/target/aarch64.c
+++ b/src/target/aarch64.c
@@ -2883,9 +2883,9 @@ static int aarch64_jim_configure(struct target *target,
struct jim_getopt_info *
pc = (struct aarch64_private_config *)target->private_config;
if (!pc) {
- pc = calloc(1, sizeof(struct aarch64_private_config));
- pc->adiv5_config.ap_num = DP_APSEL_INVALID;
- target->private_config = pc;
+ pc = calloc(1, sizeof(struct aarch64_private_config));
+ pc->adiv5_config.ap_num = DP_APSEL_INVALID;
+ target->private_config = pc;
}
/*
diff --git a/src/target/arc.c b/src/target/arc.c
index 72e4d918de..b13f3e7daf 100644
--- a/src/target/arc.c
+++ b/src/target/arc.c
@@ -388,7 +388,7 @@ static int arc_build_reg_cache(struct target *target)
}
list_for_each_entry(reg_desc, &arc->aux_reg_descriptions, list) {
- CHECK_RETVAL(arc_init_reg(target, ®_list[i], reg_desc, i));
+ CHECK_RETVAL(arc_init_reg(target, ®_list[i], reg_desc, i));
LOG_DEBUG("reg n=%3li name=%3s group=%s feature=%s", i,
reg_list[i].name, reg_list[i].group,
@@ -464,7 +464,7 @@ static int arc_build_bcr_reg_cache(struct target *target)
}
list_for_each_entry(reg_desc, &arc->bcr_reg_descriptions, list) {
- CHECK_RETVAL(arc_init_reg(target, ®_list[i], reg_desc,
gdb_regnum));
+ CHECK_RETVAL(arc_init_reg(target, ®_list[i], reg_desc,
gdb_regnum));
/* BCRs always semantically, they are just read-as-zero, if
there is
* not real register. */
reg_list[i].exist = true;
@@ -719,14 +719,14 @@ static int arc_configure(struct target *target)
LOG_DEBUG("Configuring ARC ICCM and DCCM");
/* Configuring DCCM if DCCM_BUILD and AUX_DCCM are known registers. */
- if (arc_reg_get_by_name(target->reg_cache, "dccm_build", true) &&
- arc_reg_get_by_name(target->reg_cache, "aux_dccm", true))
- CHECK_RETVAL(arc_configure_dccm(target));
+ if (arc_reg_get_by_name(target->reg_cache, "dccm_build", true)
+ && arc_reg_get_by_name(target->reg_cache, "aux_dccm", true))
+ CHECK_RETVAL(arc_configure_dccm(target));
/* Configuring ICCM if ICCM_BUILD and AUX_ICCM are known registers. */
- if (arc_reg_get_by_name(target->reg_cache, "iccm_build", true) &&
- arc_reg_get_by_name(target->reg_cache, "aux_iccm", true))
- CHECK_RETVAL(arc_configure_iccm(target));
+ if (arc_reg_get_by_name(target->reg_cache, "iccm_build", true)
+ && arc_reg_get_by_name(target->reg_cache, "aux_iccm",
true))
+ CHECK_RETVAL(arc_configure_iccm(target));
return ERROR_OK;
}
@@ -1064,12 +1064,9 @@ static int arc_poll(struct target *target)
target->state = TARGET_HALTED;
CHECK_RETVAL(target_call_event_callbacks(target,
TARGET_EVENT_HALTED));
} else {
- LOG_DEBUG("Discrepancy of STATUS32[0] HALT bit and
ARC_JTAG_STAT_RU, "
- "target is still running");
+ LOG_DEBUG("Discrepancy of STATUS32[0] HALT bit and
ARC_JTAG_STAT_RU, target is still running");
}
-
} else if (target->state == TARGET_DEBUG_RUNNING) {
-
target->state = TARGET_HALTED;
LOG_DEBUG("ARC core is in debug running mode");
@@ -1678,7 +1675,7 @@ static int arc_unset_breakpoint(struct target *target,
}
breakpoint->is_set = false;
- } else if (breakpoint->type == BKPT_HARD) {
+ } else if (breakpoint->type == BKPT_HARD) {
struct arc_common *arc = target_to_arc(target);
struct arc_actionpoint *ap_list = arc->actionpoints_list;
unsigned int bp_num = breakpoint->number;
@@ -1701,8 +1698,8 @@ static int arc_unset_breakpoint(struct target *target,
breakpoint->unique_id, bp_num);
}
} else {
- LOG_DEBUG("ERROR: unsetting unknown breakpoint type");
- return ERROR_FAIL;
+ LOG_DEBUG("ERROR: unsetting unknown breakpoint type");
+ return ERROR_FAIL;
}
return retval;
diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index 1886d5e1f6..692cde1a48 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -1287,11 +1287,11 @@ int arm_get_gdb_reg_list(struct target *target,
*reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
for (i = 0; i < 16; i++)
- (*reg_list)[i] = arm_reg_current(arm, i);
+ (*reg_list)[i] = arm_reg_current(arm, i);
/* For GDB compatibility, take FPA registers size into account
and zero-fill it*/
for (i = 16; i < 24; i++)
- (*reg_list)[i] = &arm_gdb_dummy_fp_reg;
+ (*reg_list)[i] = &arm_gdb_dummy_fp_reg;
(*reg_list)[24] = &arm_gdb_dummy_fps_reg;
(*reg_list)[25] = arm->cpsr;
@@ -1316,25 +1316,25 @@ int arm_get_gdb_reg_list(struct target *target,
*reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
for (i = 0; i < 16; i++)
- (*reg_list)[i] = arm_reg_current(arm, i);
+ (*reg_list)[i] = arm_reg_current(arm, i);
for (i = 13; i < ARRAY_SIZE(arm_core_regs); i++) {
- int reg_index =
arm->core_cache->reg_list[i].number;
+ int reg_index = arm->core_cache->reg_list[i].number;
- if (arm_core_regs[i].mode == ARM_MODE_MON
+ if (arm_core_regs[i].mode == ARM_MODE_MON
&& arm->core_type !=
ARM_CORE_TYPE_SEC_EXT
&& arm->core_type !=
ARM_CORE_TYPE_VIRT_EXT)
- continue;
- if (arm_core_regs[i].mode == ARM_MODE_HYP
+ continue;
+ if (arm_core_regs[i].mode == ARM_MODE_HYP
&& arm->core_type !=
ARM_CORE_TYPE_VIRT_EXT)
- continue;
- (*reg_list)[reg_index] =
&(arm->core_cache->reg_list[i]);
+ continue;
+ (*reg_list)[reg_index] = &arm->core_cache->reg_list[i];
}
/* When we supply the target description, there is no need for
fake FPA */
for (i = 16; i < 24; i++) {
- (*reg_list)[i] = &arm_gdb_dummy_fp_reg;
- (*reg_list)[i]->size = 0;
+ (*reg_list)[i] = &arm_gdb_dummy_fp_reg;
+ (*reg_list)[i]->size = 0;
}
(*reg_list)[24] = &arm_gdb_dummy_fps_reg;
(*reg_list)[24]->size = 0;
diff --git a/src/target/armv7a_mmu.c b/src/target/armv7a_mmu.c
index c4d294eae3..43b5dae8ef 100644
--- a/src/target/armv7a_mmu.c
+++ b/src/target/armv7a_mmu.c
@@ -260,8 +260,7 @@ COMMAND_HANDLER(armv7a_mmu_dump_table)
/* skip empty entries in the first level table */
if ((first_lvl_descriptor & 3) == 0) {
pt_idx++;
- } else
- if ((first_lvl_descriptor & 0x40002) == 2) {
+ } else if ((first_lvl_descriptor & 0x40002) == 2) {
/* section descriptor */
uint32_t va_range = 1024*1024-1; /* 1MB range */
uint32_t va_start = pt_idx << 20;
@@ -273,8 +272,7 @@ COMMAND_HANDLER(armv7a_mmu_dump_table)
LOG_USER("SECT: VA[%8.8"PRIx32" -- %8.8"PRIx32"]:
PA[%8.8"PRIx32" -- %8.8"PRIx32"] %s",
va_start, va_end, pa_start, pa_end,
l1_desc_bits_to_string(first_lvl_descriptor, afe));
pt_idx++;
- } else
- if ((first_lvl_descriptor & 0x40002) == 0x40002) {
+ } else if ((first_lvl_descriptor & 0x40002) == 0x40002) {
/* supersection descriptor */
uint32_t va_range = 16*1024*1024-1; /* 16MB range */
uint32_t va_start = pt_idx << 20;
@@ -310,8 +308,7 @@ COMMAND_HANDLER(armv7a_mmu_dump_table)
if ((second_lvl_descriptor & 3) == 0) {
/* skip entry */
pt2_idx++;
- } else
- if ((second_lvl_descriptor & 3) == 1) {
+ } else if ((second_lvl_descriptor & 3) == 1) {
/* large page */
uint32_t va_range = 64*1024-1; /* 64KB
range */
uint32_t va_start = (pt_idx << 20) +
(pt2_idx << 12);
diff --git a/src/target/armv8.c b/src/target/armv8.c
index b54ef13d37..04680e5606 100644
--- a/src/target/armv8.c
+++ b/src/target/armv8.c
@@ -1972,7 +1972,7 @@ int armv8_get_gdb_reg_list(struct target *target,
*reg_list = malloc(sizeof(struct reg *) *
(*reg_list_size));
for (i = 0; i < *reg_list_size; i++)
- (*reg_list)[i] = armv8_reg_current(arm,
i);
+ (*reg_list)[i] = armv8_reg_current(arm, i);
return ERROR_OK;
case REG_CLASS_ALL:
@@ -1980,7 +1980,7 @@ int armv8_get_gdb_reg_list(struct target *target,
*reg_list = malloc(sizeof(struct reg *) *
(*reg_list_size));
for (i = 0; i < *reg_list_size; i++)
- (*reg_list)[i] = armv8_reg_current(arm,
i);
+ (*reg_list)[i] = armv8_reg_current(arm, i);
return ERROR_OK;
diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
index 2de77c9602..ca3a5f2678 100644
--- a/src/target/cortex_a.c
+++ b/src/target/cortex_a.c
@@ -1325,21 +1325,21 @@ static int cortex_a_set_breakpoint(struct target
*target,
brp_list[brp_i].value);
} else if (breakpoint->type == BKPT_SOFT) {
uint8_t code[4];
- /* length == 2: Thumb breakpoint */
- if (breakpoint->length == 2)
+ if (breakpoint->length == 2) {
+ /* length == 2: Thumb breakpoint */
buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11));
- else
- /* length == 3: Thumb-2 breakpoint, actual encoding is
- * a regular Thumb BKPT instruction but we replace a
- * 32bit Thumb-2 instruction, so fix-up the breakpoint
- * length
- */
- if (breakpoint->length == 3) {
+ } else if (breakpoint->length == 3) {
+ /* length == 3: Thumb-2 breakpoint, actual encoding is
+ * a regular Thumb BKPT instruction but we replace a
+ * 32bit Thumb-2 instruction, so fix-up the breakpoint
+ * length
+ */
buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11));
breakpoint->length = 4;
- } else
+ } else {
/* length == 4, normal ARM breakpoint */
buf_set_u32(code, 0, 32, ARMV5_BKPT(0x11));
+ }
retval = target_read_memory(target,
breakpoint->address & 0xFFFFFFFE,
@@ -1349,8 +1349,7 @@ static int cortex_a_set_breakpoint(struct target *target,
return retval;
/* make sure data cache is cleaned & invalidated down to PoC */
- armv7a_cache_flush_virt(target, breakpoint->address,
- breakpoint->length);
+ armv7a_cache_flush_virt(target, breakpoint->address,
breakpoint->length);
retval = target_write_memory(target,
breakpoint->address & 0xFFFFFFFE,
@@ -1359,10 +1358,8 @@ static int cortex_a_set_breakpoint(struct target *target,
return retval;
/* update i-cache at breakpoint location */
- armv7a_l1_d_cache_inval_virt(target, breakpoint->address,
- breakpoint->length);
- armv7a_l1_i_cache_inval_virt(target, breakpoint->address,
- breakpoint->length);
+ armv7a_l1_d_cache_inval_virt(target, breakpoint->address,
breakpoint->length);
+ armv7a_l1_i_cache_inval_virt(target, breakpoint->address,
breakpoint->length);
breakpoint->is_set = true;
}
diff --git a/src/target/mips32.c b/src/target/mips32.c
index 81faab72da..f94a901d46 100644
--- a/src/target/mips32.c
+++ b/src/target/mips32.c
@@ -2311,7 +2311,7 @@ COMMAND_HANDLER(mips32_handle_scan_delay_command)
if (CMD_ARGC == 1)
COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], ejtag_info->scan_delay);
else if (CMD_ARGC > 1)
- return ERROR_COMMAND_SYNTAX_ERROR;
+ return ERROR_COMMAND_SYNTAX_ERROR;
command_print(CMD, "scan delay: %d nsec", ejtag_info->scan_delay);
if (ejtag_info->scan_delay >= MIPS32_SCAN_DELAY_LEGACY_MODE) {
diff --git a/src/target/mips64.c b/src/target/mips64.c
index 48f4563dc6..fb55defc08 100644
--- a/src/target/mips64.c
+++ b/src/target/mips64.c
@@ -333,7 +333,7 @@ int mips64_save_context(struct target *target)
return retval;
for (unsigned i = 0; i < MIPS64_NUM_REGS; i++)
- retval = mips64->read_core_reg(target, i);
+ retval = mips64->read_core_reg(target, i);
return retval;
}
diff --git a/src/target/mips_m4k.c b/src/target/mips_m4k.c
index ad98089614..1543de355e 100644
--- a/src/target/mips_m4k.c
+++ b/src/target/mips_m4k.c
@@ -1397,7 +1397,7 @@ COMMAND_HANDLER(mips_m4k_handle_scan_delay_command)
if (CMD_ARGC == 1)
COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], ejtag_info->scan_delay);
else if (CMD_ARGC > 1)
- return ERROR_COMMAND_SYNTAX_ERROR;
+ return ERROR_COMMAND_SYNTAX_ERROR;
command_print(CMD, "scan delay: %d nsec", ejtag_info->scan_delay);
if (ejtag_info->scan_delay >= MIPS32_SCAN_DELAY_LEGACY_MODE) {
diff --git a/src/target/stm8.c b/src/target/stm8.c
index 227101b6f0..38f6951dac 100644
--- a/src/target/stm8.c
+++ b/src/target/stm8.c
@@ -689,15 +689,13 @@ static int stm8_write_flash(struct target *target, enum
mem_type type,
if (stm8->flash_ncr2)
stm8_write_u8(target, stm8->flash_ncr2, ~(PRG +
opt));
blocksize = blocksize_param;
- } else
- if ((bytecnt >= 4) && ((address & 0x3) == 0)) {
+ } else if ((bytecnt >= 4) && ((address & 0x3) == 0)) {
if (stm8->flash_cr2)
stm8_write_u8(target, stm8->flash_cr2, WPRG +
opt);
if (stm8->flash_ncr2)
stm8_write_u8(target, stm8->flash_ncr2, ~(WPRG
+ opt));
blocksize = 4;
- } else
- if (blocksize != 1) {
+ } else if (blocksize != 1) {
if (stm8->flash_cr2)
stm8_write_u8(target, stm8->flash_cr2, opt);
if (stm8->flash_ncr2)
@@ -1552,8 +1550,8 @@ static int stm8_set_watchpoint(struct target *target,
}
if (watchpoint->length != 1) {
- LOG_ERROR("Only watchpoints of length 1 are supported");
- return ERROR_TARGET_UNALIGNED_ACCESS;
+ LOG_ERROR("Only watchpoints of length 1 are supported");
+ return ERROR_TARGET_UNALIGNED_ACCESS;
}
enum hw_break_type enable = 0;
diff --git a/src/xsvf/xsvf.c b/src/xsvf/xsvf.c
index 0266c2120c..76cd320dc7 100644
--- a/src/xsvf/xsvf.c
+++ b/src/xsvf/xsvf.c
@@ -749,10 +749,10 @@ COMMAND_HANDLER(handle_xsvf_command)
int delay;
if (read(xsvf_fd, &wait_local, 1) < 0
- || read(xsvf_fd, &end, 1) < 0
- || read(xsvf_fd, delay_buf, 4) < 0) {
- do_abort = 1;
- break;
+ || read(xsvf_fd, &end, 1) < 0
+ || read(xsvf_fd, delay_buf, 4)
< 0) {
+ do_abort = 1;
+ break;
}
wait_state = xsvf_to_tap(wait_local);
--
