This is an automated email from Gerrit.
"Marek Kraus <gamelas...@outlook.com>" just uploaded a new patch set to Gerrit,
which you can find at https://review.openocd.org/c/openocd/+/8593
-- gerrit
commit 422513303fdb69e9659e0b47f6a6be18a63d650a
Author: Marek Kraus <gamelas...@outlook.com>
Date: Sat Nov 23 15:54:26 2024 +0100
tcl/target: add Bouffalo Lab BL602 and BL702L chip series support
BL602, BL702 and BL702L series of chips are sharing same architecture,
so they all need same software reset mechanism as well.
Only difference (in terms of configuration needed for JTAG) are TAP ID,
workarea address and size. This is addressed by creating bl602_common.cfg
tcl file, which contains all those common stuff between the chips.
The script is prefixed by bl602, as this was
first *publicly* available chip from Bouffalo with this architecture.
Change-Id: I5be3694927793fd3f64c9ed4ee6ded2db0d25cae
Signed-off-by: Marek Kraus <gamelas...@outlook.com>
diff --git a/tcl/target/bl602.cfg b/tcl/target/bl602.cfg
new file mode 100644
index 0000000000..0993b093e5
--- /dev/null
+++ b/tcl/target/bl602.cfg
@@ -0,0 +1,27 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Bouffalo Labs BL602 and BL604 target
+#
+# https://en.bouffalolab.com/product/?type=detail&id=1
+#
+# Default JTAG pins: (if not changed by eFuse configuration)
+# TDO - GPIO11
+# TMS - GPIO12
+# TCK - GPIO14
+# TDI - GPIO17
+#
+
+if { [info exists CHIPNAME] } {
+ set BL602_CHIPNAME $CHIPNAME
+} else {
+ set BL602_CHIPNAME bl602
+}
+
+set CPUTAPID 0x20000c05
+
+# For work-area we use DTCM instead of ITCM, due ITCM is used as buffer for L1
cache and XIP
+set WORKAREAADDR 0x42014000
+set WORKAREASIZE 0xC000
+
+source [find target/bl602_common.cfg]
diff --git a/tcl/target/bl602_common.cfg b/tcl/target/bl602_common.cfg
new file mode 100644
index 0000000000..a4376760da
--- /dev/null
+++ b/tcl/target/bl602_common.cfg
@@ -0,0 +1,82 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Script for Bouffalo chips with similar architecture used in BL602
+# based on SiFive E21 core
+
+source [find mem_helper.tcl]
+
+transport select jtag
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ error "you must specify a tap id"
+}
+
+if { [info exists BL602_CHIPNAME] } {
+ set _CHIPNAME $BL602_CHIPNAME
+} else {
+ error "you must specify a chip name"
+}
+
+if { [info exists WORKAREAADDR] } {
+ set _WORKAREAADDR $WORKAREAADDR
+} else {
+ error "you must specify a work area address"
+}
+
+if { [info exists WORKAREASIZE] } {
+ set _WORKAREASIZE $WORKAREASIZE
+} else {
+ error "you must specify a work area size"
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+
+riscv set_mem_access sysbus
+
+$_TARGETNAME configure -work-area-phys $_WORKAREAADDR -work-area-size
$_WORKAREASIZE -work-area-backup 1
+
+# Internal RC ticks on 32 MHz, so this speed should be safe to use.
+adapter speed 8000
+
+# Debug Module's ndmreset resets only Trust Zone Controller, so we need to do
SW reset instead.
+# CTRL_PWRON_RESET triggers full "power-on like" reset.
+# This means that pinmux configuration to access JTAG is reset as well, and
configured back early
+# in BootROM.
+$_TARGETNAME configure -event reset-assert-pre {
+ halt
+
+ # Switch clock to internal RC32M
+ # In HBN_GLB, set ROOT_CLK_SEL = 0
+ mmw 0x4000f030 0x0 0x00000003
+ # Wait for clock switch
+ sleep 10
+
+ # GLB_REG_BCLK_DIS_FALSE
+ mww 0x40000ffc 0x0
+
+ # HCLK is RC32M, so BCLK/HCLK doesn't need divider
+ # In GLB_CLK_CFG0, set BCLK_DIV = 0 and HCLK_DIV = 0
+ mmw 0x40000000 0x0 0x00FFFF00
+ # Wait for clock to stabilize
+ sleep 10
+
+ # Do reset
+ # In GLB_SWRST_CFG2, clear CTRL_SYS_RESET, CTRL_CPU_RESET and
CTRL_PWRON_RESET
+ mmw 0x40000018 0x0 0x00000007
+
+ # Since this full software reset resets GPIO pinmux as well, we will
lose access
+ # to JTAG right away after writing to register. This chip doesn't
support abstract
+ # memory access, so when this is done by progbuf or sysbus, OpenOCD
will fail to read
+ # if write was successful or not, and will print error about that.
Since receiving of
+ # this error is expected, we will turn off log printing for a moment,
+ set lvl [lindex [debug_level] 1]
+ debug_level -1
+ # In GLB_SWRST_CFG2, set CTRL_SYS_RESET, CTRL_CPU_RESET and
CTRL_PWRON_RESET to 1
+ catch {mmw 0x40000018 0x7 0x0}
+ debug_level $lvl
+}
diff --git a/tcl/target/bl702.cfg b/tcl/target/bl702.cfg
index 5046cd189a..fcf4fc4eb8 100644
--- a/tcl/target/bl702.cfg
+++ b/tcl/target/bl702.cfg
@@ -12,62 +12,16 @@
# TDO - GPIO9
#
-source [find mem_helper.tcl]
-
-transport select jtag
-
if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
+ set BL602_CHIPNAME $CHIPNAME
} else {
- set _CHIPNAME bl702
+ set BL602_CHIPNAME bl702
}
-jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000e05
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME riscv -chain-position $_TARGETNAME
-
-riscv set_mem_access sysbus
-
-$_TARGETNAME configure -work-area-phys 0x22020000 -work-area-size 0x10000
-work-area-backup 1
-
-# Internal RC ticks on 32 MHz, so this speed should be safe to use.
-adapter speed 4000
+set CPUTAPID 0x20000e05
-# Debug Module's ndmreset resets only Trust Zone Controller, so we need to do
SW reset instead.
-# CTRL_PWRON_RESET triggers full "power-on like" reset.
-# This means that pinmux configuration to access JTAG is reset as well, and
configured back early
-# in BootROM.
-$_TARGETNAME configure -event reset-assert-pre {
- halt
+# For work-area we use DTCM instead of ITCM, due ITCM is used as buffer for L1
cache and XIP
+set WORKAREAADDR 0x22014000
+set WORKAREASIZE 0xC000
- # Switch clock to internal RC32M
- # In HBN_GLB, set ROOT_CLK_SEL = 0
- mmw 0x4000f030 0x0 0x00000003
- # Wait for clock switch
- sleep 10
-
- # GLB_REG_BCLK_DIS_FALSE
- mww 0x40000ffc 0x0
-
- # HCLK is RC32M, so BCLK/HCLK doesn't need divider
- # In GLB_CLK_CFG0, set BCLK_DIV = 0 and HCLK_DIV = 0
- mmw 0x40000000 0x0 0x00FFFF00
- # Wait for clock to stabilize
- sleep 10
-
- # Do reset
- # In GLB_SWRST_CFG2, clear CTRL_SYS_RESET, CTRL_CPU_RESET and
CTRL_PWRON_RESET
- mmw 0x40000018 0x0 0x00000007
-
- # Since this full software reset resets GPIO pinmux as well, we will
lose access
- # to JTAG right away after writing to register. This chip doesn't
support abstract
- # memory access, so when this is done by progbuf or sysbus, OpenOCD
will fail to read
- # if write was successful or not, and will print error about that.
Since receiving of
- # this error is expected, we will turn off log printing for a moment,
- set lvl [lindex [debug_level] 1]
- debug_level -1
- # In GLB_SWRST_CFG2, set CTRL_SYS_RESET, CTRL_CPU_RESET and
CTRL_PWRON_RESET to 1
- catch {mmw 0x40000018 0x7 0x0}
- debug_level $lvl
-}
+source [find target/bl602_common.cfg]
diff --git a/tcl/target/bl702l.cfg b/tcl/target/bl702l.cfg
new file mode 100644
index 0000000000..2059ef59fb
--- /dev/null
+++ b/tcl/target/bl702l.cfg
@@ -0,0 +1,28 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Bouffalo Labs BL702L and BL704L target
+#
+# https://en.bouffalolab.com/product/?type=detail&id=26
+#
+# Default JTAG pins: (if not changed by eFuse configuration)
+# TMS - GPIO0
+# TDI - GPIO1
+# TCK - GPIO2
+# TDO - GPIO7
+#
+
+if { [info exists CHIPNAME] } {
+ set BL602_CHIPNAME $CHIPNAME
+} else {
+ set BL602_CHIPNAME bl702l
+}
+
+set CPUTAPID 0x20000e05
+
+# For work-area we use beginning of OCRAM, since BL702L have only ITCM, which
can be taken
+# by L1 cache and XIP during runtime.
+set WORKAREAADDR 0x42020000
+set WORKAREASIZE 0x10000
+
+source [find target/bl602_common.cfg]
--
