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"Gabriel Volpicelli <gabe.volpice...@synaptics.com>" just uploaded a new patch
set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8687
-- gerrit
commit 281ac84f956f9baf13ca8bb3e86a896bf2230f57
Author: Gabriel Volpicelli <gabe.volpice...@synaptics.com>
Date: Thu Jan 2 10:33:05 2025 -0800
target: arm926ejs Resolve Unable to set 32 bit software breakpoint
The arm926ejs_write_memory function calls armv4_5_mmu_write_physical to
write directly to physical memory for 32 and 16 bit writes.
When it does so, it bypasses the dcache. For these writes, the dcache
must be invalidated, even if the dcache is in write-through mode.
If the dcache is not invalidated after these physical writes, then
software breakpoints will not function correctly for any code page that
is already in the dcache. This produces the "Unable to set 32 bit
software breakpoint at address" error message.
The sequence of events is:
1: arm7_9_common.c writes the breakpoint instruction to memory.
2: arm926ejs.c performs the write with a physical write directly to RAM.
3: The cache is now incoherent.
4: arm7_9_common.c reads the instruction back to verify it.
5: arm926ejs.c performs the read via the incoherent cache.
This commit adds a dcache invalidate to the code path that uses
armv4_5_mmu_write_physical for the MVA that was written.
Another potential solution is to modify the arm926ejs_write_memory
function to always perform a non-pysical write and utilize the dcache
write-through but this was not tested.
Change-Id: I658141d6826e3f34e2abd8aface35d4297a77e58
Signed-off-by: Gabriel Volpicelli <gabe.volpice...@synaptics.com>
diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c
index add90c9978..8cf6519f16 100644
--- a/src/target/arm926ejs.c
+++ b/src/target/arm926ejs.c
@@ -621,6 +621,19 @@ int arm926ejs_write_memory(struct target *target,
target_addr_t address,
retval = armv4_5_mmu_write_physical(target,
&arm926ejs->armv4_5_mmu, pa, size, count, buffer);
if (retval != ERROR_OK)
return retval;
+
+ /* We just wrote directly to physical memory bypassing the
cache.
+ * If DCache is enabled, then the line must be invalidated,
even in write-through mode */
+ if (arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) {
+ /* Invalidate data cache
+ *
+ * MCR p15,0,p,c7,c6,1 - invalidate cache line using
virtual address
+ *
+ */
+ retval = arm926ejs->write_cp15(target, 0, 1, 7, 6,
address & ~0x3);
+ if (retval != ERROR_OK)
+ return retval;
+ }
} else {
retval = arm7_9_write_memory(target, address, size, count,
buffer);
if (retval != ERROR_OK)
--
