This is an automated email from Gerrit.
"Adrien Charruel <acharr...@nanoxplore.com>" just uploaded a new patch set to
Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8715
-- gerrit
commit 32c1219885ffe97eb6437f92d9fb1add606a28de
Author: Ahmed BOUDJELIDA <aboudjel...@nanoxplore.com>
Date: Thu Dec 12 10:17:25 2024 +0100
contrib/firmware/angie: add new spartan6 VHDL code
This new code implement two FIFOs for handling TX and RX
JTAG data transfers, its simply receives data and send it
OUT to target chip in respect of JTAG protocol timing
constraints.
The IN FIFO receives data from target chip and send it
back to openocd.
Change-Id: I17c1231e7f4b0a6b510359fe147b609922e0809e
Signed-off-by: Ahmed BOUDJELIDA <aboudjel...@nanoxplore.com>
diff --git a/contrib/firmware/angie/hdl/src/angie_bitstream.vhd
b/contrib/firmware/angie/hdl/src/angie_bitstream.vhd
index e794eeda92..a1b86862db 100644
--- a/contrib/firmware/angie/hdl/src/angie_bitstream.vhd
+++ b/contrib/firmware/angie/hdl/src/angie_bitstream.vhd
@@ -7,15 +7,14 @@
-- Tool versions: ISE Webpack 13.2 -> 14.2
-- Author: Ahmed BOUDJELIDA nanoXplore SAS
----------------------------------------------------------------------------
-
+library work;
+use work.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-library UNISIM;
-use UNISIM.VComponents.all;
-entity S609 is port(
+entity angie_bitstream is port(
SDA_IO : inout std_logic;
SDA_DIR_I : in std_logic;
SCL_I : in std_logic;
@@ -41,41 +40,34 @@ entity S609 is port(
SI_TDO_I : in std_logic;
PA2_I : in std_logic; -- GPIF IN
--- PA3_I : in std_logic; -- GPIF OUT
-- Clock 48MHz
IFCLK_I : in std_logic;
GCTL0_I : in std_logic;
--- GCTL1_I : in std_logic;
--- GCTL2_I : in std_logic;
GRDY1_I : out std_logic;
GD_IO : inout std_logic_vector(7 downto 0);
- FTP_O : out std_logic_vector(7 downto 0)
+ FTP_O : out std_logic_vector(15 downto 0)
);
-end S609;
+end angie_bitstream;
-architecture A_S609 of S609 is
+architecture A_angie_bitstream of angie_bitstream is
----------------------------------------Fifo out (PC to devkit)
-signal clk_wr_o, clk_rd_o : std_logic;
-signal rst_o, wr_o, write_en_o, read_en_o : std_logic;
+signal rst_o, clk_wr_o, clk_rd_o : std_logic;
+signal write_en_o, read_en_o : std_logic;
signal data_in_o, data_out_o : std_logic_vector(7 downto 0);
--- signal WR_ERR_o, RD_ERR_o : std_logic;
signal empty_o, full_o : std_logic;
-signal read_clk_o : std_logic;
+
----------------------------------------Fifo in (devkit to PC)
-signal clk_wr_i, clk_rd_i : std_logic;
-signal rst_i, rd_i, write_en_i, read_en_i : std_logic;
+signal rst_i, clk_wr_i, clk_rd_i : std_logic;
+signal write_en_i, read_en_i : std_logic;
signal data_in_i, data_out_i : std_logic_vector(7 downto 0);
--- signal WR_ERR_i, RD_ERR_i : std_logic;
signal empty_i, full_i : std_logic;
-signal read_clk_i : std_logic;
-signal transit1, transit2 : std_logic;
+signal wr_o, rd_i : std_logic;
-----------------------------------------counter to 16
--- signal clk_count, rst_count, enable_count : std_logic;
--- signal count : std_logic_vector(6 downto 0);
+----------------------------------------MAE
+signal transit1, transit2 : std_logic;
----------------------------------------DFF
signal pa2_dff_clk, pa2_dff_rst, pa2_dff_d, pa2_dff_q : std_logic;
@@ -94,10 +86,6 @@ type State_Type is (IDLE, WRITE_OUT, WRITE_IN, DELAY,
READ_IN);
signal state, state2 : State_Type;
signal reset_mae, reset_mae2 : std_logic;
-----------------------------------------DCM
--- signal DCM_CLK_IN, DCM_RST, DCM_CLK_OUT : STD_LOGIC;
--- signal DCM_MUL : integer;
-
-- Add Component DFF
component DFF
Port (
@@ -118,63 +106,21 @@ Port (
end component;
-- Add component FIFO 64B
-component fifo_64b_async_dwsre
---component fifo_64b
- Port (
- --clk : in std_logic;
- clk_wr : in std_logic;
- clk_rd : in std_logic;
- rst : in std_logic;
- wr : in std_logic;
- data_in : in std_logic_vector(7 downto 0);
- write_en : in std_logic;
- -- WR_ERR : out std_logic;
- data_out : out std_logic_vector(7 downto 0);
- read_en : in std_logic;
- -- RD_ERR : out std_logic;
- empty : out std_logic;
- full : out std_logic
- );
+component fifo_generator_v9_3
+PORT (
+ rst : IN STD_LOGIC;
+ wr_clk : IN STD_LOGIC;
+ rd_clk : IN STD_LOGIC;
+ din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+ wr_en : IN STD_LOGIC;
+ rd_en : IN STD_LOGIC;
+ dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+ full : OUT STD_LOGIC;
+ empty : OUT STD_LOGIC
+ );
end component;
--- Add component FIFO 64B
-component fifo_64b_async_swdre
---component fifo_64b
- Port (
- --clk : in std_logic;
- clk_wr : in std_logic;
- clk_rd : in std_logic;
- rst : in std_logic;
- rd : in std_logic;
- data_in : in std_logic_vector(7 downto 0);
- write_en : in std_logic;
- -- WR_ERR : out std_logic;
- data_out : out std_logic_vector(7 downto 0);
- read_en : in std_logic;
- -- RD_ERR : out std_logic;
- empty : out std_logic;
- full : out std_logic
- );
-end component;
-
--- Add component counter to 16
--- component counter_to_16
--- Port (
--- clk : in STD_LOGIC;
--- reset : in STD_LOGIC;
--- clock_en : in std_logic;
--- count : out STD_LOGIC_VECTOR(6 downto 0)
--- );
--- end component;
-
--- Add component DCM
--- component dcm
--- Port ( CLK_IN : in STD_LOGIC;
--- RST : in STD_LOGIC;
--- MUL : in integer;
--- CLK_OUT : out STD_LOGIC
--- );
--- end component;
+signal state1_debug, state2_debug : std_logic;
begin
-------------------------------------------------------------I2C :
@@ -184,6 +130,7 @@ ST_5_O <= SDA_DIR_I;
SO_SCL_O <= SCL_I when (JPW_I = '1') else '0';
ST_4_O <= '0';
+
------------------------------------------------------------JTAG :
-- Instantiate the Clk div by 10
clk_div_inst : clk_div
@@ -250,60 +197,32 @@ port map (
);
-- Instantiate the FIFO OUT
-FIFO_O_inst : fifo_64b_async_dwsre
+U0 : fifo_generator_v9_3
port map (
- clk_wr => clk_wr_o,
- clk_rd => clk_rd_o,
rst => rst_o,
- wr => wr_o,
- data_in => data_in_o,
- write_en => write_en_o,
- -- WR_ERR => WR_ERR_o,
- data_out => data_out_o,
- read_en => read_en_o,
- -- RD_ERR => RD_ERR_o,
- empty => empty_o,
- full => full_o
+ wr_clk => clk_wr_o,
+ rd_clk => clk_rd_o,
+ din => data_in_o,
+ wr_en => write_en_o,
+ rd_en => read_en_o,
+ dout => data_out_o,
+ full => full_o,
+ empty => empty_o
);
-- Instantiate the FIFO IN
-FIFO_I_inst : fifo_64b_async_swdre
+U1 : fifo_generator_v9_3
port map (
- clk_wr => clk_wr_i,
- clk_rd => clk_rd_i,
rst => rst_i,
- rd => rd_i,
- data_in => data_in_i,
- write_en => write_en_i,
- -- WR_ERR => WR_ERR_i,
- data_out => data_out_i,
- read_en => read_en_i,
- -- RD_ERR => RD_ERR_i,
- empty => empty_i,
- full => full_i
+ wr_clk => clk_wr_i,
+ rd_clk => clk_rd_i,
+ din => data_in_i,
+ wr_en => write_en_i,
+ rd_en => read_en_i,
+ dout => data_out_i,
+ full => full_i,
+ empty => empty_i
);
--- Instantiate the counter
--- COUNT_inst : counter_to_16
--- port map (
--- clk => clk_count,
--- reset => rst_count,
--- clock_en => enable_count,
--- count => count
--- );
-
--- Instantiate DCM
--- DCM_inst : dcm
--- Port map(
--- CLK_IN => DCM_CLK_IN,
--- RST => DCM_RST,
--- MUL => DCM_MUL,
--- CLK_OUT => DCM_CLK_OUT
--- );
-
--------------------------------- clock :
---------------- DCM
--- DCM_CLK_IN <= clk_div2_out;
--- DCM_MUL <= 4;
--------------- clock dividers
clk_div_in <= IFCLK_I; -- 48Mhz
clk_div2_in <= clk_div_out; -- 24Mhz
@@ -322,9 +241,6 @@ clk_rd_o <= clk_div2_out;
clk_wr_i <= clk_div2_out;
clk_rd_i <= IFCLK_I;
---------------- Counter
---clk_count <= IFCLK_I;
-
--------------------------- GPIF ready :
GRDY1_I <= '1';
@@ -332,14 +248,14 @@ GRDY1_I <= '1';
pa2_dff_rst <= '0';
pa2_dff_d <= PA2_I;
--------------------- Fifos Enable pins :
-write_en_o <= GCTL0_I;
-read_en_i <= GCTL0_I;
+-------------------- FX2<->Fifo Enable pins :
+write_en_o <= not(wr_o) and not(GCTL0_I);
+read_en_i <= not(rd_i) and not(GCTL0_I);
----------------- GDx Input to FIFO OUT :
+---------------- FX2->Fifo Data :
data_in_o <= GD_IO;
------------- FIFO OUT output to devkit :
+------------ FIFO_OUT->Devkit :
SO_TRST_O <= trst_q;
trst_d <= data_out_o(4);
SO_TMS_O <= tms_q;
@@ -349,13 +265,10 @@ tdi_d <= data_out_o(1);
------------
SO_TCK_O <= data_out_o(0);
------------------- FIFO OUT to FIFO IN :
+-------------------- FIFO_OUT->FIFO_IN :
--data_in_i <= data_out_o;
-------------------- Counter to FIFO IN :
---data_in_i(6 downto 0) <= count;
-
--------------------- Devkit to FIFO IN :
+-------------------- FIFO_IN<-Devkit :
data_in_i(0) <= '0';
data_in_i(1) <= '0';
data_in_i(2) <= tdo_q;
@@ -366,18 +279,21 @@ data_in_i(5) <= '0';
data_in_i(6) <= '0';
data_in_i(7) <= '0';
-------------------- FIFO IN to Cypress :
+-------------------- FX2<-FIFO_IN :
GD_IO <= data_out_i when (state = READ_IN) else "ZZZZZZZZ";
+state1_debug <= '1' when state = READ_IN else '0';
+state2_debug <= '1' when state2 = WRITE_IN else '0';
+
--Points de test:
-FTP_O(0) <= data_out_o(4);
-FTP_O(1) <= data_out_o(0);
-FTP_O(2) <= data_out_o(3);
-FTP_O(3) <= not SI_TDO_I;
-FTP_O(4) <= PA2_I;
-FTP_O(5) <= empty_o;
-FTP_O(6) <= SI_TDO_I;
-FTP_O(7) <= data_out_o(1);
+FTP_O(0) <= IFCLK_I;
+FTP_O(1) <= GCTL0_I;
+FTP_O(2) <= GD_IO(0);
+FTP_O(3) <= GD_IO(1);
+FTP_O(4) <= JPW_I;
+FTP_O(5) <= PA2_I;
+FTP_O(6) <= empty_o;
+FTP_O(7) <= not SI_TDO_I;
process(pa2_dff_d, pa2_dff_q)
begin
@@ -386,7 +302,6 @@ begin
reset_mae2 <= '1'; -- Reset State Machine
rst_o <= '1'; -- Reset OUT
rst_i <= '1'; -- Reset IN
- -- DCM_RST <= '1';
reset_clk_div <= '1';
reset_clk_div2 <= '1';
trst_rst <= '1';
@@ -394,13 +309,11 @@ begin
tdi_rst <= '1';
tdo_rst <= '1';
srst_rst <= '1';
- -- rst_count <= '1';
else
reset_mae <= '0'; -- No Reset State Machine
reset_mae2 <= '0'; -- Reset State Machine
rst_o <= '0'; -- No Reset OUT
rst_i <= '0'; -- No Reset IN
- -- DCM_RST <= '0';
reset_clk_div <= '0';
reset_clk_div2 <= '0';
trst_rst <= '0';
@@ -408,7 +321,6 @@ begin
tdi_rst <= '0';
tdo_rst <= '0';
srst_rst <= '0';
- --rst_count <= '0';
end if;
end process;
@@ -419,28 +331,29 @@ begin
elsif rising_edge(clk_div2_out) then
case state2 is
when IDLE =>
- read_en_o <= '1'; -- Disable read OUT
- write_en_i <= '1'; -- Disable write IN
+ read_en_o <= '0'; -- Disable read OUT
+ write_en_i <= '0'; -- Disable write IN
transit2 <= '1';
- if transit1 = '0' then
+ if transit1 = '0' and PA2_I = '0' then
state2 <= WRITE_IN;
+ else
+ state2 <= IDLE;
end if;
when WRITE_IN =>
- read_en_o <= '0'; -- Enable read OUT
- write_en_i <= '0'; -- Enable write IN
- if empty_o = '1' then
+ read_en_o <= '1'; -- Enable read OUT
+ write_en_i <= '1'; -- Enable write IN
+ if PA2_I = '1' then
state2 <= DELAY; -- Change state to DELAY
else
state2 <= WRITE_IN; -- Stay in WRITE_IN state
end if;
when DELAY =>
- read_en_o <= '1'; -- Disable read OUT
- write_en_i <= '1'; -- Disable write IN
- --enable_count <= '1'; -- Disable Counter
- if PA2_I = '1' then
- transit2 <= '0'; -- Enable READ IN
+ transit2 <= '0'; -- Enable READ IN
+ if empty_o = '1' then
+ read_en_o <= '0'; --
Disable read OUT
+ write_en_i <= '0'; --
Disable write IN
state2 <= IDLE; -- Change state to IDLE
else
state2 <= DELAY; -- Stay in READ_IN state
@@ -512,4 +425,4 @@ SO_SRST_O <= '0';
-- MOD : in
ST_3_O <= '1';
-end A_S609;
+end A_angie_bitstream;
diff --git a/contrib/firmware/angie/hdl/src/clk_div.vhd
b/contrib/firmware/angie/hdl/src/clk_div.vhd
index c8310dabf0..e69850d572 100644
--- a/contrib/firmware/angie/hdl/src/clk_div.vhd
+++ b/contrib/firmware/angie/hdl/src/clk_div.vhd
@@ -1,13 +1,3 @@
--- SPDX-License-Identifier: BSD-3-Clause
-----------------------------------------------------------------------------
--- Project Context: nanoXplore USB to JTAG/I2C Adapter Board, Spartan6
--- Design Name: Clock divider
--- Module Name: angie_bitstream.vhd
--- Target Device: XC6SLX9-2 TQ144
--- Tool versions: ISE Webpack 13.2 -> 14.2
--- Author: Ahmed BOUDJELIDA nanoXplore SAS
-----------------------------------------------------------------------------
-
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
@@ -40,4 +30,4 @@ begin
end if;
end process;
clk_out <= tmp;
-end behavioral;
+end behavioral;
\ No newline at end of file
diff --git a/contrib/firmware/angie/hdl/src/dff.vhd
b/contrib/firmware/angie/hdl/src/dff.vhd
index b0c194651f..c5ccf06d33 100644
--- a/contrib/firmware/angie/hdl/src/dff.vhd
+++ b/contrib/firmware/angie/hdl/src/dff.vhd
@@ -1,13 +1,3 @@
--- SPDX-License-Identifier: BSD-3-Clause
-----------------------------------------------------------------------------
--- Project Context: nanoXplore USB to JTAG/I2C Adapter Board, Spartan6
--- Design Name: DFF
--- Module Name: angie_bitstream.vhd
--- Target Device: XC6SLX9-2 TQ144
--- Tool versions: ISE Webpack 13.2 -> 14.2
--- Author: Ahmed BOUDJELIDA nanoXplore SAS
-----------------------------------------------------------------------------
-
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_arith.ALL;
@@ -30,4 +20,4 @@ begin
q <= d; -- Capture D at the rising edge of the clock
end if;
end process;
-end Behavioral;
+end Behavioral;
\ No newline at end of file
--
