This is an automated email from Gerrit.
"Tomas Vanek <van...@fbl.cz>" just uploaded a new patch set to Gerrit, which
you can find at https://review.openocd.org/c/openocd/+/8741
-- gerrit
commit 1f089fb9ca924b0ed3925d29349b31490faea0cc
Author: Tomas Vanek <van...@fbl.cz>
Date: Sat Feb 8 18:46:32 2025 +0100
doc: warn about CH347T problems
Tell potential users that buying CH347T is not the best idea.
Change-Id: Id6557909fcb56a1e95e16277c1cd7df6769cf4dd
Signed-off-by: Tomas Vanek <van...@fbl.cz>
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 51219414c2..74fc9dbba5 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -2545,6 +2545,27 @@ and a specific set of GPIOs is used.
@deffn {Interface Driver} {ch347}
Driver for WCH CH347T chips in mode 3 (UART + JTAG).
+
+@b{WARNING:} WCH CH347T chips have unbelievably poor performance
+with respect to the USB HS connection.
+@itemize @bullet
+@item Chip version 2.41:
+@itemize @minus
+@item JTAG timing is very weird, some clock pulses are
+much shorter then the requested clock frequency.
+@item SWD is not implemented.
+@end itemize
+@item Chip version 4.41:
+@itemize @minus
+@item SWD clock is limited to maximum 1 MHz.
+@item SWD reading AP reg CH347 erroneously drives
+SWDIO to H for 392 ns after the last ACK bit. Some devices get so upset
+that send wrong data with parity error. A resistor in the SWDIO circuit
+mitigates the problem.
+@item A long SWD operation causes that USB host disconnects the adapter.
+@end itemize
+@end itemize
+
This driver has these driver-specific command:
@deffn {Config Command} {ch347 vid_pid} vid pid
--
