[PATCH]: a3875f63b9 tcl/target: Add Renesas R-Car Gen4 R8A779G0 V4H and R8A779H0 V4M targets

[gerrit]

This is an automated email from Gerrit.

"Marek Vasut <marek.va...@gmail.com>" just uploaded a new patch set to Gerrit, 
which you can find at https://review.openocd.org/c/openocd/+/8807

-- gerrit

commit a3875f63b90ce0d6f80b74bb8c57e5185c2a3662
Author: Marek Vasut <marek.va...@gmail.com>
Date:   Fri Aug 23 01:29:12 2024 +0200

    tcl/target: Add Renesas R-Car Gen4 R8A779G0 V4H and R8A779H0 V4M targets
    
    Add support for Renesas R-Car Gen4 R8A779G0 V4H and R8A779H0 V4M SoCs.
    Those contain 4x CA76 and 3x CR52 cores.
    
    Change-Id: I4a701f0fec4dd574fc099a221d464ccc55db6252
    Signed-off-by: Marek Vasut <marek.va...@gmail.com>

diff --git a/tcl/target/renesas_rcar_gen3.cfg b/tcl/target/renesas_rcar_gen3.cfg
index 73b3003a94..f6bc5e4c8f 100644
--- a/tcl/target/renesas_rcar_gen3.cfg
+++ b/tcl/target/renesas_rcar_gen3.cfg
@@ -90,6 +90,18 @@ switch $_soc {
                set _num_cr52 1
                set _boot_core CA76
        }
+       V4H {
+               set _CHIPNAME r8a779g0
+               set _num_ca76 4
+               set _num_cr52 3
+               set _boot_core CR52
+       }
+       V4M {
+               set _CHIPNAME r8a779h0
+               set _num_ca76 4
+               set _num_cr52 3
+               set _boot_core CR52
+       }
        default {
                error "'$_soc' is invalid!"
        }
@@ -126,8 +138,8 @@ set CA57_DBGBASE {0x80410000 0x80510000 0x80610000 
0x80710000}
 set CA57_CTIBASE {0x80420000 0x80520000 0x80620000 0x80720000}
 set CA53_DBGBASE {0x80C10000 0x80D10000 0x80E10000 0x80F10000}
 set CA53_CTIBASE {0x80C20000 0x80D20000 0x80E20000 0x80F20000}
-set CR52_DBGBASE 0x80c10000
-set CR52_CTIBASE 0x80c20000
+set CR52_DBGBASE {0x80C10000 0x80D10000 0x80E10000}
+set CR52_CTIBASE {0x80C20000 0x80D20000 0x80E20000}
 set  CR7_DBGBASE 0x80910000
 set  CR7_CTIBASE 0x80918000
 
@@ -159,24 +171,27 @@ proc setup_a5x {core_name dbgbase ctibase num boot} {
 proc setup_crx {core_name dbgbase ctibase num boot} {
        global _CHIPNAME
        global _DAPNAME
+       global smp_targets
        global _targets
        for { set _core 0 } { $_core < $num } { incr _core } {
-               set _TARGETNAME $_CHIPNAME.$core_name
+               set _TARGETNAME $_CHIPNAME.$core_name.$_core
                set _CTINAME $_TARGETNAME.cti
-               cti create $_CTINAME -dap $_DAPNAME -ap-num 1 -baseaddr $ctibase
+               cti create $_CTINAME -dap $_DAPNAME -ap-num 1 -baseaddr [lindex 
$ctibase $_core]
                if { $core_name == "r52" } {
                        set _command "target create $_TARGETNAME armv8r -dap 
$_DAPNAME \
-                               -ap-num 1 -dbgbase $dbgbase -cti $_CTINAME"
+                               -ap-num 1 -dbgbase [lindex $dbgbase $_core] 
-cti $_CTINAME"
                } else {
                        set _command "target create $_TARGETNAME cortex_r4 -dap 
$_DAPNAME \
-                               -ap-num 1 -dbgbase $dbgbase"
+                               -ap-num 1 -dbgbase [lindex $dbgbase $_core]"
                }
-               if { $boot == 1 } {
+               if { $_core == 0 && $boot == 1 } {
                        set _targets "$_TARGETNAME"
                } else {
                        set _command "$_command -defer-examine"
                }
+               set smp_targets "$smp_targets $_TARGETNAME"
                eval $_command
+               $_TARGETNAME configure -event examine-end { halt }
        }
 }
 

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