This is an automated email from Gerrit.
"Junhui Liu <junhui....@pigmoral.tech>" just uploaded a new patch set to
Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8821
-- gerrit
commit 75e19e0fbae3162699a585e1e85f521e69ed6d25
Author: Junhui Liu <junhui....@pigmoral.tech>
Date: Wed Mar 26 23:05:39 2025 +0800
tcl/target: Add RCPU support for Spacemit K1
Add support for the Real-Time CPU (RCPU) of K1, which is a 32-bit RISC-V
N308 High-Efficiency Processor Core designed by Nuclei System Technology
Co. Ltd.
The JTAG interface can be configured to connect to either X60s or RCPU
processors. To enable JTAG for RCPU, set TARGET to "rcpu".
For example:
openocd -c "set TARGET rcpu" -f interface/cmsis-dap.cfg \
-f target/spacemit-k1.cfg
Change-Id: I9cd62fac332137afac17efa52702818de8f0b6f5
Signed-off-by: Junhui Liu <junhui....@pigmoral.tech>
diff --git a/tcl/target/spacemit-k1.cfg b/tcl/target/spacemit-k1.cfg
index ef5d7833dd..cf03e7ad08 100644
--- a/tcl/target/spacemit-k1.cfg
+++ b/tcl/target/spacemit-k1.cfg
@@ -10,6 +10,21 @@ transport select jtag
adapter speed 2000
+# Set TARGET to "rcpu" to enable JTAG for RCPU
+if { [info exists TARGET] } {
+ set _TARGET $TARGET
+} else {
+ set _TARGET x60
+}
+
+if { $_TARGET == "rcpu" } {
+ set CPUTAPID 0x10308A6D
+ set DRVAL 0xe
+} else {
+ set CPUTAPID 0x10000E21
+ set DRVAL 0xa
+}
+
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
@@ -23,21 +38,21 @@ if { [info exists CORES] } {
}
if { [info exists SECJTAG] } {
- jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10000E21
+ jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $CPUTAPID
} else {
jtag newtap pre unknown -irlen 1 -expected-id 0x00000000 -disable
jtag configure pre.unknown -event tap-enable ""
- jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10000E21 -disable
+ jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $CPUTAPID -disable
jtag configure $_CHIPNAME.cpu -event tap-enable ""
jtag newtap post unknown -irlen 9 -expected-id 0x08501C0D -ignore-version
jtag configure post.unknown -event setup {
- global _CHIPNAME
+ global _CHIPNAME DRVAL
irscan post.unknown 0x98
- drscan post.unknown 16 0xa
+ drscan post.unknown 16 $DRVAL
jtag tapenable pre.unknown
jtag tapenable $_CHIPNAME.cpu
@@ -45,22 +60,27 @@ if { [info exists SECJTAG] } {
}
set _TARGETNAME $_CHIPNAME.cpu
-set DBGBASE {0x0 0x400}
-set _smp_command "target smp"
-for { set _core 0 } { $_core < $_cores } { incr _core } {
- target create $_TARGETNAME.$_core riscv -chain-position $_TARGETNAME \
- -coreid [expr {$_core % 4}] -dbgbase [lindex $DBGBASE [expr {$_core /
4}]]
+if { $_TARGET == "rcpu" } {
+ target create $_TARGETNAME.0 riscv -chain-position $_CHIPNAME.cpu
+} else {
+ set DBGBASE {0x0 0x400}
+ set _smp_command "target smp"
+
+ for { set _core 0 } { $_core < $_cores } { incr _core } {
+ target create $_TARGETNAME.$_core riscv -chain-position $_TARGETNAME \
+ -coreid [expr {$_core % 4}] -dbgbase [lindex $DBGBASE [expr
{$_core / 4}]]
- if { [expr {$_core % 4}] == 0 } {
- $_TARGETNAME.$_core configure -rtos hwthread
+ if { [expr {$_core % 4}] == 0 } {
+ $_TARGETNAME.$_core configure -rtos hwthread
+ }
+
+ set _smp_command "$_smp_command $_TARGETNAME.$_core"
}
- set _smp_command "$_smp_command $_TARGETNAME.$_core"
+ eval $_smp_command
}
-eval $_smp_command
-
set _SPEED 8000
$_TARGETNAME.0 configure -event examine-start {
--
