This is an automated email from Gerrit.
"zapb <d...@zapb.de>" just uploaded a new patch set to Gerrit, which you can
find at https://review.openocd.org/c/openocd/+/8863
-- gerrit
commit 01539da37b19399004536152ac3047c9b80b67d5
Author: Marc Schink <d...@zapb.de>
Date: Mon Apr 21 17:46:05 2025 +0000
tcl/target: Move nordic configuration files
Move target configuration files into a dedicated vendor directory as
required by the new guideline for configuration files.
Change-Id: Ia1d06b5a8a646d65f2cdc5a9415df3014a93b7d7
Signed-off-by: Marc Schink <d...@zapb.de>
diff --git a/tcl/target/nrf_common.cfg b/tcl/target/nordic/common.cfg
similarity index 100%
rename from tcl/target/nrf_common.cfg
rename to tcl/target/nordic/common.cfg
diff --git a/tcl/target/nordic/nrf51.cfg b/tcl/target/nordic/nrf51.cfg
new file mode 100644
index 0000000000..3781eccb50
--- /dev/null
+++ b/tcl/target/nordic/nrf51.cfg
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# script for Nordic nRF51 series, a Cortex-M0 chip
+#
+
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME nrf51
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 16kB
+if { [info exists WORKAREASIZE] } {
+ set _WORKAREASIZE $WORKAREASIZE
+} else {
+ set _WORKAREASIZE 0x4000
+}
+
+if { [info exists CPUTAPID] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ set _CPUTAPID 0x0bb11477
+}
+
+swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size
$_WORKAREASIZE -work-area-backup 0
+
+if {![using_hla]} {
+ # The chip supports standard ARM/Cortex-M0 SYSRESETREQ signal
+ cortex_m reset_config sysresetreq
+}
+
+flash bank $_CHIPNAME.flash nrf5 0x00000000 0 0 0 $_TARGETNAME
+flash bank $_CHIPNAME.uicr nrf5 0x10001000 0 0 0 $_TARGETNAME
+
+# The chip should start up from internal 16Mhz RC, so setting adapter
+# clock to 1Mhz should be OK
+adapter speed 1000
+
+proc enable_all_ram {} {
+ # nRF51822 Product Anomaly Notice (PAN) #16 explains that not all RAM
banks
+ # are reliably enabled after reset on some revisions (contrary to
spec.) So after
+ # resetting we enable all banks via the RAMON register
+ mww 0x40000524 0xF
+}
+$_TARGETNAME configure -event reset-init { enable_all_ram }
diff --git a/tcl/target/nordic/nrf52.cfg b/tcl/target/nordic/nrf52.cfg
new file mode 100644
index 0000000000..0703b18862
--- /dev/null
+++ b/tcl/target/nordic/nrf52.cfg
@@ -0,0 +1,184 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Nordic nRF52 series: ARM Cortex-M4 @ 64 MHz
+#
+
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME nrf52
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 16kB
+if { [info exists WORKAREASIZE] } {
+ set _WORKAREASIZE $WORKAREASIZE
+} else {
+ set _WORKAREASIZE 0x4000
+}
+
+if { [info exists CPUTAPID] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ set _CPUTAPID 0x2ba01477
+}
+
+swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
+
+adapter speed 1000
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size
$_WORKAREASIZE -work-area-backup 0
+
+if { [using_hla] } {
+ echo ""
+ echo "nRF52 device has a CTRL-AP dedicated to recover the device from
AP lock."
+ echo "A high level adapter (like a ST-Link) you are currently using
cannot access"
+ echo "the CTRL-AP so 'nrf52_recover' command will not work."
+ echo "Do not enable UICR APPROTECT."
+ echo ""
+} else {
+ cortex_m reset_config sysresetreq
+
+ $_TARGETNAME configure -event examine-fail nrf52_check_ap_lock
+}
+
+flash bank $_CHIPNAME.flash nrf5 0x00000000 0 1 1 $_TARGETNAME
+flash bank $_CHIPNAME.uicr nrf5 0x10001000 0 1 1 $_TARGETNAME
+
+# Test if MEM-AP is locked by UICR APPROTECT
+proc nrf52_check_ap_lock {} {
+ set dap [[target current] cget -dap]
+ set err [catch {set APPROTECTSTATUS [$dap apreg 1 0xc]}]
+ if {$err == 0 && $APPROTECTSTATUS != 1} {
+ echo "****** WARNING ******"
+ echo "nRF52 device has AP lock engaged (see UICR APPROTECT
register)."
+ echo "Debug access is denied."
+ echo "Use 'nrf52_recover' to erase and unlock the device."
+ echo ""
+ poll off
+ }
+}
+
+# Mass erase and unlock the device using proprietary nRF CTRL-AP (AP #1)
+# http://www.ebyte.com produces modules with nRF52 locked by default,
+# use nrf52_recover to enable flashing and debug.
+proc nrf52_recover {} {
+ set target [target current]
+ set dap [$target cget -dap]
+
+ set IDR [$dap apreg 1 0xfc]
+ if {$IDR != 0x02880000} {
+ echo "Error: Cannot access nRF52 CTRL-AP!"
+ return
+ }
+
+ poll off
+
+ # Reset and trigger ERASEALL task
+ $dap apreg 1 4 0
+ $dap apreg 1 4 1
+
+ for {set i 0} {1} {incr i} {
+ set ERASEALLSTATUS [$dap apreg 1 8]
+ if {$ERASEALLSTATUS == 0} {
+ echo "$target device has been successfully erased and
unlocked."
+ break
+ }
+ if {$i == 0} {
+ echo "Waiting for chip erase..."
+ }
+ if {$i >= 150} {
+ echo "Error: $target recovery failed."
+ break
+ }
+ sleep 100
+ }
+
+ # Assert reset
+ $dap apreg 1 0 1
+
+ # Deassert reset
+ $dap apreg 1 0 0
+
+ # Reset ERASEALL task
+ $dap apreg 1 4 0
+
+ sleep 100
+ $target arp_examine
+ poll on
+}
+
+add_help_text nrf52_recover "Mass erase and unlock nRF52 device"
+
+tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
+
+lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu
+proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname _chipname} {
+ targets $_targetname
+
+ # Read FICR.INFO.PART
+ set PART [mrw 0x10000100]
+
+ switch $PART {
+ 0x52840 -
+ 0x52833 -
+ 0x52832 {
+ # Configuration values for all supported trace port
speeds, see
+ # TRACECONFIG.TRACEPORTSPEED
+ set trace_port_speeds {
+ 32000000 0
+ 16000000 1
+ 8000000 2
+ 4000000 3
+ }
+
+ # Note that trace port clock stands for what is
referred to as
+ # TRACECLKIN in the Arm CoreSight documentation.
+ set trace_port_clock [$_chipname.tpiu cget -traceclk]
+
+ if { ![dict exists $trace_port_speeds
$trace_port_clock] } {
+ error "Trace clock speed is not supported"
+ }
+
+ # Set TRACECONFIG.TRACEPORTSPEED
+ mmw 0x4000055C [dict get $trace_port_speeds
$trace_port_clock] 0x3
+
+ if { [$_chipname.tpiu cget -protocol] eq "sync" } {
+ if { [$_chipname.tpiu cget -port-width] != 4 } {
+ error "Device only supports 4-bit sync
traces"
+ }
+
+ # Set TRACECONFIG.TRACEMUX to enable
synchronous trace
+ mmw 0x4000055C 0x00020000 0x00010000
+ $_targetname configure -event reset-end {
+ mmw 0x4000055C 0x00020000 0x00010000
+ }
+ } else {
+ # Set TRACECONFIG.TRACEMUX to enable SWO
+ mmw 0x4000055C 0x00010000 0x00020000
+ $_targetname configure -event reset-end {
+ mmw 0x4000055C 0x00010000 0x00020000
+ }
+ }
+ }
+ 0x52820 -
+ 0x52811 -
+ 0x52810 -
+ 0x52805 {
+ error "Device does not support TPIU"
+ }
+ default {
+ error "Unknown device, cannot configure TPIU"
+ }
+ }
+}
+
+$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu
$_TARGETNAME $_CHIPNAME"
diff --git a/tcl/target/nordic/nrf53.cfg b/tcl/target/nordic/nrf53.cfg
new file mode 100644
index 0000000000..0dcfd55eca
--- /dev/null
+++ b/tcl/target/nordic/nrf53.cfg
@@ -0,0 +1,146 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Nordic nRF53 series: dual ARM Cortex-M33, multidrop SWD
+#
+
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME nrf53
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 16kB
+if { [info exists WORKAREASIZE] } {
+ set _WORKAREASIZE $WORKAREASIZE
+} else {
+ set _WORKAREASIZE 0x4000
+}
+
+if { [info exists CPUTAPID] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ set _CPUTAPID 0x6ba02477
+}
+
+# Configurable instance ID resides in application UICR TINSTANCE
+if { [info exists SWD_INSTANCE_ID] } {
+ set _SWD_INSTANCE_ID $SWD_INSTANCE_ID
+} else {
+ set _SWD_INSTANCE_ID 0
+}
+
+swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
+
+if { [info exists SWD_MULTIDROP] } {
+ dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu -dp-id
0x0070289 -instance-id $_SWD_INSTANCE_ID
+} else {
+ dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+}
+
+set _TARGETNAME_APP $_CHIPNAME.cpuapp
+target create $_TARGETNAME_APP cortex_m -dap $_CHIPNAME.dap
+
+$_TARGETNAME_APP configure -work-area-phys 0x20000000 -work-area-size
$_WORKAREASIZE -work-area-backup 0
+
+# The network core is not accessible over HLA
+if { ![using_hla] } {
+ set _TARGETNAME_NET $_CHIPNAME.cpunet
+ target create $_TARGETNAME_NET cortex_m -dap $_CHIPNAME.dap -ap-num 1
-defer-examine
+
+ targets $_TARGETNAME_APP
+
+ $_TARGETNAME_NET configure -work-area-phys 0x21000000 -work-area-size
$_WORKAREASIZE -work-area-backup 0
+}
+
+# Keep adapter speed less or equal 2000 kHz or flash programming fails!
+adapter speed 1000
+
+source [find target/nordic/common.cfg]
+
+flash bank $_CHIPNAME.app.flash nrf5 0x00000000 0 0 0 $_TARGETNAME_APP
+flash bank $_CHIPNAME.app.uicr nrf5 0x00FF8000 0 0 0 $_TARGETNAME_APP
+
+if { ![using_hla] } {
+
+ flash bank $_CHIPNAME.net.flash nrf5 0x01000000 0 0 0 $_TARGETNAME_NET
+ flash bank $_CHIPNAME.net.uicr nrf5 0x01FF8000 0 0 0 $_TARGETNAME_NET
+
+ # System reset sets NETWORK.FORCEOFF which keeps the network core in
reset
+ # Don't touch network core during reset
+ $_TARGETNAME_NET configure -event reset-assert {}
+ # and start it after application core reset is finished to make all
flash accessible
+ $_TARGETNAME_APP configure -event reset-init "nrf53_cpunet_release
$_CHIPNAME"
+
+ $_TARGETNAME_APP cortex_m reset_config sysresetreq
+ $_TARGETNAME_NET cortex_m reset_config sysresetreq
+
+ $_TARGETNAME_APP configure -event examine-fail { _nrf_check_ap_lock 2 3
}
+ $_TARGETNAME_NET configure -event examine-fail { _nrf_check_ap_lock 3 3
}
+
+ $_TARGETNAME_NET configure -event gdb-attach "_nrf53_cpunet_gdb_attach
$_CHIPNAME"
+
+ proc _nrf53_cpunet_gdb_attach { _CHIPNAME } {
+ set _TARGETNAME_APP $_CHIPNAME.cpuapp
+ set _TARGETNAME_NET $_CHIPNAME.cpunet
+ set RESET_NETWORK_FORCEOFF 0x50005614
+
+ set is_off [$_TARGETNAME_APP read_memory
$RESET_NETWORK_FORCEOFF 32 1]
+ if { $is_off } {
+ nrf53_cpunet_release $_CHIPNAME
+ $_TARGETNAME_NET arp_poll
+ $_TARGETNAME_NET arp_waitstate halted 100
+ } else {
+ if { ![$_TARGETNAME_NET was_examined] } {
+ $_TARGETNAME_NET arp_examine
+ $_TARGETNAME_NET arp_poll
+ }
+ set s [$_TARGETNAME_NET curstate]
+ if { ![string compare $s "halted"] } {
+ halt
+ }
+ }
+ }
+ lappend _telnet_autocomplete_skip _nrf53_cpunet_gdb_attach
+
+ # Release the network core
+ proc nrf53_cpunet_release { {_CHIPNAME nrf53} } {
+ set _TARGETNAME_APP $_CHIPNAME.cpuapp
+ set _TARGETNAME_NET $_CHIPNAME.cpunet
+ set RESET_NETWORK_FORCEOFF 0x50005614
+ set RESET_NETWORK_WORKAROUND 0x50005618
+ set CORTEX_M_DCB_DEMCR 0xE000EDFC
+
+ $_TARGETNAME_APP mww $RESET_NETWORK_WORKAROUND 1
+ $_TARGETNAME_APP mww $RESET_NETWORK_FORCEOFF 0
+ $_TARGETNAME_APP mww $RESET_NETWORK_FORCEOFF 1
+ set err [catch {$_TARGETNAME_NET arp_examine}]
+ if { $err } {
+ if { ![_nrf_check_ap_lock 3 3] } {
+ echo "Error: \[$_TARGETNAME_NET\] examination
failed"
+ }
+ return
+ }
+ # set TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET
+ $_TARGETNAME_NET mww $CORTEX_M_DCB_DEMCR 0x01000501
+ # Write DEMCR directly intead of permanetly setting by cortex_m
vector_catch reset
+ # following cortex_m_endreset_event() restores the original
DEMCR value
+ $_TARGETNAME_APP mww $RESET_NETWORK_FORCEOFF 0
+ $_TARGETNAME_APP mww $RESET_NETWORK_WORKAROUND 0
+ }
+
+ # Mass erase and unlock the device using proprietary nRF CTRL-AP (AP #2
or #3)
+ proc nrf53_cpuapp_recover {} {
+ _nrf_ctrl_ap_recover 2
+ }
+ add_help_text nrf53_cpuapp_recover "Mass erase flash and unlock nRF53
application CPU"
+
+ proc nrf53_recover {} {
+ _nrf_ctrl_ap_recover 3 1
+ }
+ add_help_text nrf53_recover "Mass erase all device flash and unlock
nRF53"
+}
diff --git a/tcl/target/nordic/nrf91.cfg b/tcl/target/nordic/nrf91.cfg
new file mode 100644
index 0000000000..64ed864e75
--- /dev/null
+++ b/tcl/target/nordic/nrf91.cfg
@@ -0,0 +1,63 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Nordic nRF91 series: ARM Cortex-M33, SWD only
+#
+
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME nrf91
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 16kB
+if { [info exists WORKAREASIZE] } {
+ set _WORKAREASIZE $WORKAREASIZE
+} else {
+ set _WORKAREASIZE 0x4000
+}
+
+if { [info exists CPUTAPID] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ set _CPUTAPID 0x6ba02477
+}
+
+swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
+
+# Contrary to the product specification at least nRF9161 supports multidrop
SWD.
+# The instance ID is fixed, no more than one nRF91 can be connected to one SWD
bus.
+if { [info exists SWD_MULTIDROP] } {
+ dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu -dp-id
0x0090289 -instance-id 0
+} else {
+ dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
+
+# Keep adapter speed less or equal 2000 kHz or flash programming fails!
+adapter speed 1000
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size
$_WORKAREASIZE -work-area-backup 0
+
+source [find target/nordic/common.cfg]
+
+flash bank $_CHIPNAME.flash nrf5 0x00000000 0 0 0 $_TARGETNAME
+flash bank $_CHIPNAME.uicr nrf5 0x00FF8000 0 0 0 $_TARGETNAME
+
+if { ![using_hla] } {
+ $_TARGETNAME cortex_m reset_config sysresetreq
+
+ $_TARGETNAME configure -event examine-fail { _nrf_check_ap_lock 4 3 }
+}
+
+# Mass erase and unlock the device using proprietary nRF CTRL-AP (AP #4)
+proc nrf91_recover {} {
+ _nrf_ctrl_ap_recover 4
+}
+add_help_text nrf91_recover "Mass erase and unlock nRF91 device"
diff --git a/tcl/target/nrf51.cfg b/tcl/target/nrf51.cfg
index 3781eccb50..097d1d8970 100644
--- a/tcl/target/nrf51.cfg
+++ b/tcl/target/nrf51.cfg
@@ -1,61 +1,5 @@
# SPDX-License-Identifier: GPL-2.0-or-later
-#
-# script for Nordic nRF51 series, a Cortex-M0 chip
-#
+echo "WARNING: 'target/nrf51.cfg' is deprecated, use 'target/nordic/nrf51.cfg'
instead"
-source [find target/swj-dp.tcl]
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME nrf51
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-# Work-area is a space in RAM used for flash programming
-# By default use 16kB
-if { [info exists WORKAREASIZE] } {
- set _WORKAREASIZE $WORKAREASIZE
-} else {
- set _WORKAREASIZE 0x4000
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x0bb11477
-}
-
-swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
-dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
-
-$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size
$_WORKAREASIZE -work-area-backup 0
-
-if {![using_hla]} {
- # The chip supports standard ARM/Cortex-M0 SYSRESETREQ signal
- cortex_m reset_config sysresetreq
-}
-
-flash bank $_CHIPNAME.flash nrf5 0x00000000 0 0 0 $_TARGETNAME
-flash bank $_CHIPNAME.uicr nrf5 0x10001000 0 0 0 $_TARGETNAME
-
-# The chip should start up from internal 16Mhz RC, so setting adapter
-# clock to 1Mhz should be OK
-adapter speed 1000
-
-proc enable_all_ram {} {
- # nRF51822 Product Anomaly Notice (PAN) #16 explains that not all RAM
banks
- # are reliably enabled after reset on some revisions (contrary to
spec.) So after
- # resetting we enable all banks via the RAMON register
- mww 0x40000524 0xF
-}
-$_TARGETNAME configure -event reset-init { enable_all_ram }
+source [find target/nordic/nrf51.cfg]
diff --git a/tcl/target/nrf52.cfg b/tcl/target/nrf52.cfg
index 0703b18862..637181fb09 100644
--- a/tcl/target/nrf52.cfg
+++ b/tcl/target/nrf52.cfg
@@ -1,184 +1,5 @@
# SPDX-License-Identifier: GPL-2.0-or-later
-#
-# Nordic nRF52 series: ARM Cortex-M4 @ 64 MHz
-#
+echo "WARNING: 'target/nrf52.cfg' is deprecated, use 'target/nordic/nrf52.cfg'
instead"
-source [find target/swj-dp.tcl]
-source [find mem_helper.tcl]
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME nrf52
-}
-
-# Work-area is a space in RAM used for flash programming
-# By default use 16kB
-if { [info exists WORKAREASIZE] } {
- set _WORKAREASIZE $WORKAREASIZE
-} else {
- set _WORKAREASIZE 0x4000
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x2ba01477
-}
-
-swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
-dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
-
-adapter speed 1000
-
-$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size
$_WORKAREASIZE -work-area-backup 0
-
-if { [using_hla] } {
- echo ""
- echo "nRF52 device has a CTRL-AP dedicated to recover the device from
AP lock."
- echo "A high level adapter (like a ST-Link) you are currently using
cannot access"
- echo "the CTRL-AP so 'nrf52_recover' command will not work."
- echo "Do not enable UICR APPROTECT."
- echo ""
-} else {
- cortex_m reset_config sysresetreq
-
- $_TARGETNAME configure -event examine-fail nrf52_check_ap_lock
-}
-
-flash bank $_CHIPNAME.flash nrf5 0x00000000 0 1 1 $_TARGETNAME
-flash bank $_CHIPNAME.uicr nrf5 0x10001000 0 1 1 $_TARGETNAME
-
-# Test if MEM-AP is locked by UICR APPROTECT
-proc nrf52_check_ap_lock {} {
- set dap [[target current] cget -dap]
- set err [catch {set APPROTECTSTATUS [$dap apreg 1 0xc]}]
- if {$err == 0 && $APPROTECTSTATUS != 1} {
- echo "****** WARNING ******"
- echo "nRF52 device has AP lock engaged (see UICR APPROTECT
register)."
- echo "Debug access is denied."
- echo "Use 'nrf52_recover' to erase and unlock the device."
- echo ""
- poll off
- }
-}
-
-# Mass erase and unlock the device using proprietary nRF CTRL-AP (AP #1)
-# http://www.ebyte.com produces modules with nRF52 locked by default,
-# use nrf52_recover to enable flashing and debug.
-proc nrf52_recover {} {
- set target [target current]
- set dap [$target cget -dap]
-
- set IDR [$dap apreg 1 0xfc]
- if {$IDR != 0x02880000} {
- echo "Error: Cannot access nRF52 CTRL-AP!"
- return
- }
-
- poll off
-
- # Reset and trigger ERASEALL task
- $dap apreg 1 4 0
- $dap apreg 1 4 1
-
- for {set i 0} {1} {incr i} {
- set ERASEALLSTATUS [$dap apreg 1 8]
- if {$ERASEALLSTATUS == 0} {
- echo "$target device has been successfully erased and
unlocked."
- break
- }
- if {$i == 0} {
- echo "Waiting for chip erase..."
- }
- if {$i >= 150} {
- echo "Error: $target recovery failed."
- break
- }
- sleep 100
- }
-
- # Assert reset
- $dap apreg 1 0 1
-
- # Deassert reset
- $dap apreg 1 0 0
-
- # Reset ERASEALL task
- $dap apreg 1 4 0
-
- sleep 100
- $target arp_examine
- poll on
-}
-
-add_help_text nrf52_recover "Mass erase and unlock nRF52 device"
-
-tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
-
-lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu
-proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname _chipname} {
- targets $_targetname
-
- # Read FICR.INFO.PART
- set PART [mrw 0x10000100]
-
- switch $PART {
- 0x52840 -
- 0x52833 -
- 0x52832 {
- # Configuration values for all supported trace port
speeds, see
- # TRACECONFIG.TRACEPORTSPEED
- set trace_port_speeds {
- 32000000 0
- 16000000 1
- 8000000 2
- 4000000 3
- }
-
- # Note that trace port clock stands for what is
referred to as
- # TRACECLKIN in the Arm CoreSight documentation.
- set trace_port_clock [$_chipname.tpiu cget -traceclk]
-
- if { ![dict exists $trace_port_speeds
$trace_port_clock] } {
- error "Trace clock speed is not supported"
- }
-
- # Set TRACECONFIG.TRACEPORTSPEED
- mmw 0x4000055C [dict get $trace_port_speeds
$trace_port_clock] 0x3
-
- if { [$_chipname.tpiu cget -protocol] eq "sync" } {
- if { [$_chipname.tpiu cget -port-width] != 4 } {
- error "Device only supports 4-bit sync
traces"
- }
-
- # Set TRACECONFIG.TRACEMUX to enable
synchronous trace
- mmw 0x4000055C 0x00020000 0x00010000
- $_targetname configure -event reset-end {
- mmw 0x4000055C 0x00020000 0x00010000
- }
- } else {
- # Set TRACECONFIG.TRACEMUX to enable SWO
- mmw 0x4000055C 0x00010000 0x00020000
- $_targetname configure -event reset-end {
- mmw 0x4000055C 0x00010000 0x00020000
- }
- }
- }
- 0x52820 -
- 0x52811 -
- 0x52810 -
- 0x52805 {
- error "Device does not support TPIU"
- }
- default {
- error "Unknown device, cannot configure TPIU"
- }
- }
-}
-
-$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu
$_TARGETNAME $_CHIPNAME"
+source [find target/nordic/nrf52.cfg]
diff --git a/tcl/target/nrf53.cfg b/tcl/target/nrf53.cfg
index 307df902c2..83174db98c 100644
--- a/tcl/target/nrf53.cfg
+++ b/tcl/target/nrf53.cfg
@@ -1,146 +1,5 @@
# SPDX-License-Identifier: GPL-2.0-or-later
-#
-# Nordic nRF53 series: dual ARM Cortex-M33, multidrop SWD
-#
+echo "WARNING: 'target/nrf53.cfg' is deprecated, use 'target/nordic/nrf53.cfg'
instead"
-source [find target/swj-dp.tcl]
-source [find mem_helper.tcl]
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME nrf53
-}
-
-# Work-area is a space in RAM used for flash programming
-# By default use 16kB
-if { [info exists WORKAREASIZE] } {
- set _WORKAREASIZE $WORKAREASIZE
-} else {
- set _WORKAREASIZE 0x4000
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x6ba02477
-}
-
-# Configurable instance ID resides in application UICR TINSTANCE
-if { [info exists SWD_INSTANCE_ID] } {
- set _SWD_INSTANCE_ID $SWD_INSTANCE_ID
-} else {
- set _SWD_INSTANCE_ID 0
-}
-
-swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
-
-if { [info exists SWD_MULTIDROP] } {
- dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu -dp-id
0x0070289 -instance-id $_SWD_INSTANCE_ID
-} else {
- dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
-}
-
-set _TARGETNAME_APP $_CHIPNAME.cpuapp
-target create $_TARGETNAME_APP cortex_m -dap $_CHIPNAME.dap
-
-$_TARGETNAME_APP configure -work-area-phys 0x20000000 -work-area-size
$_WORKAREASIZE -work-area-backup 0
-
-# The network core is not accessible over HLA
-if { ![using_hla] } {
- set _TARGETNAME_NET $_CHIPNAME.cpunet
- target create $_TARGETNAME_NET cortex_m -dap $_CHIPNAME.dap -ap-num 1
-defer-examine
-
- targets $_TARGETNAME_APP
-
- $_TARGETNAME_NET configure -work-area-phys 0x21000000 -work-area-size
$_WORKAREASIZE -work-area-backup 0
-}
-
-# Keep adapter speed less or equal 2000 kHz or flash programming fails!
-adapter speed 1000
-
-source [find target/nrf_common.cfg]
-
-flash bank $_CHIPNAME.app.flash nrf5 0x00000000 0 0 0 $_TARGETNAME_APP
-flash bank $_CHIPNAME.app.uicr nrf5 0x00FF8000 0 0 0 $_TARGETNAME_APP
-
-if { ![using_hla] } {
-
- flash bank $_CHIPNAME.net.flash nrf5 0x01000000 0 0 0 $_TARGETNAME_NET
- flash bank $_CHIPNAME.net.uicr nrf5 0x01FF8000 0 0 0 $_TARGETNAME_NET
-
- # System reset sets NETWORK.FORCEOFF which keeps the network core in
reset
- # Don't touch network core during reset
- $_TARGETNAME_NET configure -event reset-assert {}
- # and start it after application core reset is finished to make all
flash accessible
- $_TARGETNAME_APP configure -event reset-init "nrf53_cpunet_release
$_CHIPNAME"
-
- $_TARGETNAME_APP cortex_m reset_config sysresetreq
- $_TARGETNAME_NET cortex_m reset_config sysresetreq
-
- $_TARGETNAME_APP configure -event examine-fail { _nrf_check_ap_lock 2 3
}
- $_TARGETNAME_NET configure -event examine-fail { _nrf_check_ap_lock 3 3
}
-
- $_TARGETNAME_NET configure -event gdb-attach "_nrf53_cpunet_gdb_attach
$_CHIPNAME"
-
- proc _nrf53_cpunet_gdb_attach { _CHIPNAME } {
- set _TARGETNAME_APP $_CHIPNAME.cpuapp
- set _TARGETNAME_NET $_CHIPNAME.cpunet
- set RESET_NETWORK_FORCEOFF 0x50005614
-
- set is_off [$_TARGETNAME_APP read_memory
$RESET_NETWORK_FORCEOFF 32 1]
- if { $is_off } {
- nrf53_cpunet_release $_CHIPNAME
- $_TARGETNAME_NET arp_poll
- $_TARGETNAME_NET arp_waitstate halted 100
- } else {
- if { ![$_TARGETNAME_NET was_examined] } {
- $_TARGETNAME_NET arp_examine
- $_TARGETNAME_NET arp_poll
- }
- set s [$_TARGETNAME_NET curstate]
- if { ![string compare $s "halted"] } {
- halt
- }
- }
- }
- lappend _telnet_autocomplete_skip _nrf53_cpunet_gdb_attach
-
- # Release the network core
- proc nrf53_cpunet_release { {_CHIPNAME nrf53} } {
- set _TARGETNAME_APP $_CHIPNAME.cpuapp
- set _TARGETNAME_NET $_CHIPNAME.cpunet
- set RESET_NETWORK_FORCEOFF 0x50005614
- set RESET_NETWORK_WORKAROUND 0x50005618
- set CORTEX_M_DCB_DEMCR 0xE000EDFC
-
- $_TARGETNAME_APP mww $RESET_NETWORK_WORKAROUND 1
- $_TARGETNAME_APP mww $RESET_NETWORK_FORCEOFF 0
- $_TARGETNAME_APP mww $RESET_NETWORK_FORCEOFF 1
- set err [catch {$_TARGETNAME_NET arp_examine}]
- if { $err } {
- if { ![_nrf_check_ap_lock 3 3] } {
- echo "Error: \[$_TARGETNAME_NET\] examination
failed"
- }
- return
- }
- # set TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET
- $_TARGETNAME_NET mww $CORTEX_M_DCB_DEMCR 0x01000501
- # Write DEMCR directly intead of permanetly setting by cortex_m
vector_catch reset
- # following cortex_m_endreset_event() restores the original
DEMCR value
- $_TARGETNAME_APP mww $RESET_NETWORK_FORCEOFF 0
- $_TARGETNAME_APP mww $RESET_NETWORK_WORKAROUND 0
- }
-
- # Mass erase and unlock the device using proprietary nRF CTRL-AP (AP #2
or #3)
- proc nrf53_cpuapp_recover {} {
- _nrf_ctrl_ap_recover 2
- }
- add_help_text nrf53_cpuapp_recover "Mass erase flash and unlock nRF53
application CPU"
-
- proc nrf53_recover {} {
- _nrf_ctrl_ap_recover 3 1
- }
- add_help_text nrf53_recover "Mass erase all device flash and unlock
nRF53"
-}
+source [find target/nordic/nrf53.cfg]
diff --git a/tcl/target/nrf91.cfg b/tcl/target/nrf91.cfg
index e0ff4e5460..370fbed3ef 100644
--- a/tcl/target/nrf91.cfg
+++ b/tcl/target/nrf91.cfg
@@ -1,63 +1,5 @@
# SPDX-License-Identifier: GPL-2.0-or-later
-#
-# Nordic nRF91 series: ARM Cortex-M33, SWD only
-#
+echo "WARNING: 'target/nrf91.cfg' is deprecated, use 'target/nordic/nrf91.cfg'
instead"
-source [find target/swj-dp.tcl]
-source [find mem_helper.tcl]
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME nrf91
-}
-
-# Work-area is a space in RAM used for flash programming
-# By default use 16kB
-if { [info exists WORKAREASIZE] } {
- set _WORKAREASIZE $WORKAREASIZE
-} else {
- set _WORKAREASIZE 0x4000
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x6ba02477
-}
-
-swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
-
-# Contrary to the product specification at least nRF9161 supports multidrop
SWD.
-# The instance ID is fixed, no more than one nRF91 can be connected to one SWD
bus.
-if { [info exists SWD_MULTIDROP] } {
- dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu -dp-id
0x0090289 -instance-id 0
-} else {
- dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
-}
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
-
-# Keep adapter speed less or equal 2000 kHz or flash programming fails!
-adapter speed 1000
-
-$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size
$_WORKAREASIZE -work-area-backup 0
-
-source [find target/nrf_common.cfg]
-
-flash bank $_CHIPNAME.flash nrf5 0x00000000 0 0 0 $_TARGETNAME
-flash bank $_CHIPNAME.uicr nrf5 0x00FF8000 0 0 0 $_TARGETNAME
-
-if { ![using_hla] } {
- $_TARGETNAME cortex_m reset_config sysresetreq
-
- $_TARGETNAME configure -event examine-fail { _nrf_check_ap_lock 4 3 }
-}
-
-# Mass erase and unlock the device using proprietary nRF CTRL-AP (AP #4)
-proc nrf91_recover {} {
- _nrf_ctrl_ap_recover 4
-}
-add_help_text nrf91_recover "Mass erase and unlock nRF91 device"
+source [find target/nordic/nrf91.cfg]
--
