This is an automated email from Gerrit.
"Tomas Vanek <van...@fbl.cz>" just uploaded a new patch set to Gerrit, which
you can find at https://review.openocd.org/c/openocd/+/8918
-- gerrit
commit 7d8a6430ce8c8612bef49ae9c4d49be80fb8a963
Author: Tomas Vanek <van...@fbl.cz>
Date: Sun May 18 11:49:31 2025 +0200
flash, target: avoid logging of numeric target state
Replace it by target_state_name() helper.
Change-Id: I720f2bf121e6fd2c6987a7e8fa9e52593888ee6c
Signed-off-by: Tomas Vanek <van...@fbl.cz>
diff --git a/src/flash/nor/ambiqmicro.c b/src/flash/nor/ambiqmicro.c
index bb893778ce..67cc6b68a7 100644
--- a/src/flash/nor/ambiqmicro.c
+++ b/src/flash/nor/ambiqmicro.c
@@ -309,9 +309,9 @@ static int ambiqmicro_exec_command(struct target *target,
*/
target_poll(target);
alive_sleep(100);
- LOG_DEBUG("state = %d", target->state);
} else {
- LOG_ERROR("Target not halted or running %d",
target->state);
+ LOG_ERROR("Target not halted or running (state is %s)",
+ target_state_name(target));
break;
}
}
diff --git a/src/target/espressif/esp32.c b/src/target/espressif/esp32.c
index 399ba8e7cd..5e2490a229 100644
--- a/src/target/espressif/esp32.c
+++ b/src/target/espressif/esp32.c
@@ -192,8 +192,8 @@ static int esp32_soc_reset(struct target *target)
alive_sleep(10);
xtensa_poll(target);
if (timeval_ms() >= timeout) {
- LOG_TARGET_ERROR(target, "Timed out waiting for CPU to
be reset, target state=%d",
- target->state);
+ LOG_TARGET_ERROR(target, "Timed out waiting for CPU to
be reset, target state %s",
+ target_state_name(target));
get_timeout = true;
break;
}
diff --git a/src/target/espressif/esp32s2.c b/src/target/espressif/esp32s2.c
index b86e43e626..e32893a6b2 100644
--- a/src/target/espressif/esp32s2.c
+++ b/src/target/espressif/esp32s2.c
@@ -272,8 +272,8 @@ static int esp32s2_soc_reset(struct target *target)
alive_sleep(10);
xtensa_poll(target);
if (timeval_ms() >= timeout) {
- LOG_TARGET_ERROR(target, "Timed out waiting for CPU to
be reset, target state=%d",
- target->state);
+ LOG_TARGET_ERROR(target, "Timed out waiting for CPU to
be reset, target state %s",
+ target_state_name(target));
return ERROR_TARGET_TIMEOUT;
}
}
diff --git a/src/target/espressif/esp32s3.c b/src/target/espressif/esp32s3.c
index 82413f77fb..14f7a7bb64 100644
--- a/src/target/espressif/esp32s3.c
+++ b/src/target/espressif/esp32s3.c
@@ -193,8 +193,8 @@ static int esp32s3_soc_reset(struct target *target)
xtensa_poll(target);
if (timeval_ms() >= timeout) {
LOG_TARGET_ERROR(target,
- "Timed out waiting for CPU to be reset, target
state=%d",
- target->state);
+ "Timed out waiting for CPU to be reset, target
state %s",
+ target_state_name(target));
get_timeout = true;
break;
}
diff --git a/src/target/stm8.c b/src/target/stm8.c
index 81c41f2b2a..7785d40ef0 100644
--- a/src/target/stm8.c
+++ b/src/target/stm8.c
@@ -870,7 +870,7 @@ static int stm8_poll(struct target *target)
uint8_t csr1, csr2;
#ifdef LOG_STM8
- LOG_DEBUG("target->state=%d", target->state);
+ LOG_DEBUG("target->state %s", target_state_name(target));
#endif
/* read dm_csrx control regs */
diff --git a/src/target/xtensa/xtensa.c b/src/target/xtensa/xtensa.c
index 3a877edfa6..3366623d64 100644
--- a/src/target/xtensa/xtensa.c
+++ b/src/target/xtensa/xtensa.c
@@ -949,7 +949,8 @@ int xtensa_smpbreak_set(struct target *target, uint32_t set)
xtensa->smp_break = set;
if (target_was_examined(target))
res = xtensa_smpbreak_write(xtensa, xtensa->smp_break);
- LOG_TARGET_DEBUG(target, "set smpbreak=%" PRIx32 ", state=%i", set,
target->state);
+ LOG_TARGET_DEBUG(target, "set smpbreak=%" PRIx32 ", state %s", set,
+ target_state_name(target));
return res;
}
--
