This is an automated email from Gerrit.
"Michael Mazlin <mmich...@marvell.com>" just uploaded a new patch set to
Gerrit, which you can find at https://review.openocd.org/c/openocd/+/9103
-- gerrit
commit d83bc7a9bd93c5a6f84bf35b9e5101b7f2429871
Author: Michael Mazlin <michael_maz...@hotmail.com>
Date: Fri Aug 29 13:32:03 2025 -0700
add OlympusA files
Change-Id: Ica998f2e94bd14359671305a3e3c8f33536b3e01
Signed-off-by: Michael Mazlin <michael_maz...@hotmail.com>
diff --git a/src/jtag/drivers/OlympusA/InphiOlympus.h
b/src/jtag/drivers/OlympusA/InphiOlympus.h
index 40317df96b..1fd41c179a 100644
--- a/src/jtag/drivers/OlympusA/InphiOlympus.h
+++ b/src/jtag/drivers/OlympusA/InphiOlympus.h
@@ -878,7 +878,7 @@ typedef struct
unsigned long Size;
unsigned long PowerSupplyNumber;
- double InitialVoltage; //Specify negative value to use "Current
Voltage" as start point
+ double InitialVoltage; //Specify negative value to use "Current
Voltage" as start point
double FinalVoltage;
double RampTime; //ms
diff --git a/src/jtag/drivers/OlympusA/Zeus-1Interface.h
b/src/jtag/drivers/OlympusA/Zeus-1Interface.h
index f0bf1224d4..59e7352a28 100644
--- a/src/jtag/drivers/OlympusA/Zeus-1Interface.h
+++ b/src/jtag/drivers/OlympusA/Zeus-1Interface.h
@@ -157,32 +157,32 @@
#define DS4432_ADDR 0x90 //1001000R -
NOT USED 400 kHz
#define DS4424_ADDR_00 0x20 //A1_A0_10_000R
400 kHz
#define AD5593R_ADDR_1 0x22 //AD5593R (ZAMBONI) 400 kHz
- #define AD5593R_CONFIG_MODE 0 << 4
- #define AD5593R_ADC_SEQ_REG 0x0002
- #define AD5593R_GP_CTRL_REG 0x0003
- #define AD5593R_ADC_CFG_REG 0x0004
- #define AD5593R_DAC_CFG_REG 0x0005
- #define AD5593R_PULLDOWN_CFG_REG 0x0006
- #define AD5593R_LDAC_MODE_REG 0x0007
- #define AD5593R_GPIO_CFG_REG 0x0008
- #define AD5593R_GPIO_OUTPUT_REG 0x0009
- #define AD5593R_GPIO_INPUT_REG 0x000A
- #define AD5593R_PD_REF_REG 0x000B
- #define AD5593R_GPIO_OPENDRAIN_CFG_REG 0x000C
- #define AD5593R_TS_CFG_REG 0x000D
- #define AD5593R_SW_RESET_REG 0x000F
-
- #define AD5593R_DAC_WR 1 << 4
-
- #define AD5593R_VPELTIER_CH 0
- #define AD5593R_CUR_LIMIT_CH 1
- #define AD5593R_VFAN0_CH 2
- #define AD5593R_VFAN1_CH 3
-
- #define AD5593R_ADC_RD 4 << 4
- #define AD5593R_DAC_RD 5 << 4
- #define AD5593R_GPIO_RD 6 << 4
- #define AD5593R_REG_RD 7 << 4
+ #define AD5593R_CONFIG_MODE 0 << 4
+ #define AD5593R_ADC_SEQ_REG 0x0002
+ #define AD5593R_GP_CTRL_REG 0x0003
+ #define AD5593R_ADC_CFG_REG 0x0004
+ #define AD5593R_DAC_CFG_REG 0x0005
+ #define AD5593R_PULLDOWN_CFG_REG 0x0006
+ #define AD5593R_LDAC_MODE_REG 0x0007
+ #define AD5593R_GPIO_CFG_REG 0x0008
+ #define AD5593R_GPIO_OUTPUT_REG 0x0009
+ #define AD5593R_GPIO_INPUT_REG 0x000A
+ #define AD5593R_PD_REF_REG 0x000B
+ #define AD5593R_GPIO_OPENDRAIN_CFG_REG 0x000C
+ #define AD5593R_TS_CFG_REG 0x000D
+ #define AD5593R_SW_RESET_REG 0x000F
+
+ #define AD5593R_DAC_WR 1 << 4
+
+ #define AD5593R_VPELTIER_CH 0
+ #define AD5593R_CUR_LIMIT_CH 1
+ #define AD5593R_VFAN0_CH 2
+ #define AD5593R_VFAN1_CH 3
+
+ #define AD5593R_ADC_RD 4 << 4
+ #define AD5593R_DAC_RD 5 << 4
+ #define AD5593R_GPIO_RD 6 << 4
+ #define AD5593R_REG_RD 7 << 4
#define SHT4_ADDR_A 0x88 //Humidity Sensor (ZAMBONI)
#define SHT4_ADDR_B 0x8A //Humidity Sensor
@@ -916,23 +916,23 @@
#define SIF_CONFIG_MEMORY 0x0270
#define SIF_PORT0_INDEX0 0x0270 // 5 ADDR SIZE, 1 DATA SIZE, 2
STEP, 3 PRE, 5 WR WAIT, 5 RD WAIT, 5 WR POST, 5 RD POST = 31 - 1 Register
- #define SIF_32_ADDRESS_MASK 0x0000001F
- #define SIF_32_DATA_MASK 0x00000020
- #define SIF_STEP_SIZE_MASK 0x000000C0
- #define SIF_PRE_BITS_MASK 0x00000700
- #define SIF_WR_WAIT_BITS_MASK 0x0000F800
- #define SIF_RD_WAIT_BITS_MASK 0x001F0000
- #define SIF_WR_POST_BITS_MASK 0x03E00000
- #define SIF_RD_POST_BITS_MASK 0x7C000000
-
- #define SIF_32_ADDRESS_SHIFT 0
- #define SIF_32_DATA_SHIFT 5
- #define SIF_STEP_SIZE_SHIFT 6
- #define SIF_PRE_BITS_SHIFT 8
- #define SIF_WR_WAIT_BITS_SHIFT 11
- #define SIF_RD_WAIT_BITS_SHIFT 16
- #define SIF_WR_POST_BITS_SHIFT 21
- #define SIF_RD_POST_BITS_SHIFT 26
+ #define SIF_32_ADDRESS_MASK 0x0000001F
+ #define SIF_32_DATA_MASK 0x00000020
+ #define SIF_STEP_SIZE_MASK 0x000000C0
+ #define SIF_PRE_BITS_MASK 0x00000700
+ #define SIF_WR_WAIT_BITS_MASK 0x0000F800
+ #define SIF_RD_WAIT_BITS_MASK 0x001F0000
+ #define SIF_WR_POST_BITS_MASK 0x03E00000
+ #define SIF_RD_POST_BITS_MASK 0x7C000000
+
+ #define SIF_32_ADDRESS_SHIFT 0
+ #define SIF_32_DATA_SHIFT 5
+ #define SIF_STEP_SIZE_SHIFT 6
+ #define SIF_PRE_BITS_SHIFT 8
+ #define SIF_WR_WAIT_BITS_SHIFT 11
+ #define SIF_RD_WAIT_BITS_SHIFT 16
+ #define SIF_WR_POST_BITS_SHIFT 21
+ #define SIF_RD_POST_BITS_SHIFT 26
#define SIF_PORT0_INDEX1 0x0271
#define SIF_PORT0_INDEX2 0x0272
#define SIF_PORT0_INDEX3 0x0273
@@ -1014,14 +1014,14 @@
#define IJTAG_NUMBER_OF_TRST_N_CYCLES 8
#define IJTAG_CURRENT_CNFG_PORT0 0x76FB // 31:16 - Port 0
File ID
- // 7:0 - Port 0
Active IP
+
// 7:0 - Port 0 Active IP
#define IJTAG_CURRENT_CNFG_PORT1 0x76FC // 31:16 - Port 1
File ID
- // 7:0 - Port 0
Active IP
+
// 7:0 - Port 0 Active IP
#define IJTAG_SELECT_TRST_N_IR_LENGTH_PORT1_PORT0 0x76FD // 31:24 - Port 1
Time for TRST_N. Number of TRST_N cycles * 2 (Low + High) in IJTAG CLK
- // 23:16 - Port 0
Time for TRST_N
- // 12:8 - PORT 1
IR Command Length - 5 bits -> Up to 32 bits IR
- // 4:0 - PORT 0
IR Command Length - 5 bits -> Up to 32 bits IR
+
// 23:16 - Port 0 Time for TRST_N
+
// 12:8 - PORT 1 IR Command Length -
5 bits -> Up to 32 bits IR
+
// 4:0 - PORT 0 IR Command Length -
5 bits -> Up to 32 bits IR
#define IJTAG_SELECT_IR_DATA_PORT0 0x76FE // IR Data -> up
to 32 bits
#define IJTAG_SELECT_IR_DATA_PORT1 0x76FF // IR Data -> up
to 32 bits
--
