This is an automated email from Gerrit. "Adrien Charruel <[email protected]>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/9111
-- gerrit commit ebef2194c226231135a228bc069b3e317c447cc6 Author: Adrien Charruel <[email protected]> Date: Tue Mar 11 11:20:36 2025 +0100 target/aarch64: Add user command to flush d- and i-caches Rationale: - We need to flush caches prior to load a new binary. - Introduce a user command to do so. Change-Id: Idb54dbd2eef1c33f5ea4039d1510211db755dfb6 Signed-off-by: Adrien Charruel <[email protected]> diff --git a/src/target/aarch64.c b/src/target/aarch64.c index 5b600f0777..e1eacd9717 100644 --- a/src/target/aarch64.c +++ b/src/target/aarch64.c @@ -125,6 +125,41 @@ static int aarch64_restore_system_control_reg(struct target *target) return retval; } +static int aarch64_flush_and_deactivate_caches(struct target *target) +{ + struct aarch64_common *aarch64 = target_to_aarch64(target); + struct armv8_common *armv8 = &aarch64->armv8_common; + int retval = ERROR_OK; + uint64_t system_control_reg_curr_updated = aarch64->system_control_reg_curr; + + if (target->state != TARGET_HALTED) { + LOG_TARGET_ERROR(target, "not halted"); + return ERROR_TARGET_NOT_HALTED; + } + + if (system_control_reg_curr_updated & 0x4U) { + /* data cache is active */ + system_control_reg_curr_updated &= ~0x4U; + /* flush data cache armv8 function to be called */ + if (armv8->armv8_mmu.armv8_cache.flush_all_data_cache) + armv8->armv8_mmu.armv8_cache.flush_all_data_cache(target); + } + if (system_control_reg_curr_updated & 0x1000U) { + /* instruction cache is active */ + system_control_reg_curr_updated &= ~0x1000U; + /* flush instruction cache armv8 function to be called */ + if (armv8->armv8_mmu.armv8_cache.invalidate_all_instruction_cache) + armv8->armv8_mmu.armv8_cache.invalidate_all_instruction_cache(target); + } + + if (system_control_reg_curr_updated != aarch64->system_control_reg_curr) { + aarch64->system_control_reg_curr = system_control_reg_curr_updated; + retval = aarch64_write_system_control_reg(target, aarch64->system_control_reg_curr); + } + + return retval; +} + /* modify system_control_reg in order to enable or disable mmu for : * - virt2phys address conversion * - read or write memory in phys or virt address */ @@ -3131,6 +3166,12 @@ COMMAND_HANDLER(aarch64_mcrmrc_command) return ERROR_OK; } +COMMAND_HANDLER(aarch64_handle_clear_caches) +{ + struct target *target = get_current_target(CMD_CTX); + return aarch64_flush_and_deactivate_caches(target); +} + static const struct command_registration aarch64_exec_command_handlers[] = { { .name = "cache_info", @@ -3174,6 +3215,13 @@ static const struct command_registration aarch64_exec_command_handlers[] = { .help = "read coprocessor register", .usage = "cpnum op1 CRn CRm op2", }, + { + .name = "clear_caches", + .handler = aarch64_handle_clear_caches, + .mode = COMMAND_EXEC, + .help = "clear and invalidate instruction and data caches", + .usage = "", + }, { .chain = smp_command_handlers, }, --
