This is an automated email from Gerrit. "Peter pan <[email protected]>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/9017
-- gerrit commit bf8e8d670166245810514e9df0ef229f546017f7 Author: Jiafei Pan <[email protected]> Date: Mon Jun 9 15:09:59 2025 +0800 tcl: add imx943 target and evk board Added i.MX 943 target and EVK board support Change-Id: I3eb05da56048549c25e62a7b250e28054b44d595 Signed-off-by: Jiafei Pan <[email protected]> diff --git a/tcl/board/nxp_imx943-evk.cfg b/tcl/board/nxp_imx943-evk.cfg new file mode 100644 index 0000000000..ad701860f4 --- /dev/null +++ b/tcl/board/nxp_imx943-evk.cfg @@ -0,0 +1,25 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# configuration file for NXP MC-IMX8M-EVK +# + +# only JTAG supported +transport select jtag + +# set a safe JTAG clock speed, can be overridden +adapter speed 3000 + +# default JTAG configuration has only SRST and no TRST +reset_config srst_only srst_push_pull + +# delay after SRST goes inactive +adapter srst delay 70 + + +# board has an i.MX953 with 4 Cortex-A55 cores +set CHIPNAME imx943 +set CHIPCORES 4 + +# source SoC configuration +source [find target/imx943.cfg] diff --git a/tcl/target/imx943.cfg b/tcl/target/imx943.cfg new file mode 100644 index 0000000000..d34fd3247c --- /dev/null +++ b/tcl/target/imx943.cfg @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# configuration file for NXP i.MX943 family of SoCs +# +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME imx943 +} + +if { [info exists CHIPCORES] } { + set _cores $CHIPCORES +} else { + set _cores 1 +} + +# CoreSight Debug Access Port +if { [info exists DAP_TAPID] } { + set _DAP_TAPID $DAP_TAPID +} else { + set _DAP_TAPID 0x8893001d +} + +# the DAP tap +jtag newtap $_CHIPNAME cpu -irlen 8 -ircapture 0x01 -irmask 0xff \ + -expected-id $_DAP_TAPID + +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +set _TARGETNAME $_CHIPNAME.a55 +set _CTINAME $_CHIPNAME.cti + +set DBGBASE {0x40810000 0x40910000 0x40a10000 0x40b10000 0x40c10000 0x40d10000} +set CTIBASE {0x40820000 0x40920000 0x40a20000 0x40b20000 0x40c20000 0x40d20000} + +for { set _core 0 } { $_core < $_cores } { incr _core } { + + cti create $_CTINAME.$_core -dap $_CHIPNAME.dap -ap-num 1 \ + -baseaddr [lindex $CTIBASE $_core] + + set _command "target create $_TARGETNAME.$_core aarch64 -dap $_CHIPNAME.dap \ + -dbgbase [lindex $DBGBASE $_core] -cti $_CTINAME.$_core -coreid $_core" + + eval $_command +} + +#eval $_smp_command + +# declare the auxiliary Cortex-M4 core on AP #4 +target create ${_CHIPNAME}.m4 cortex_m -dap ${_CHIPNAME}.dap -ap-num 4 \ + -defer-examine + +# AHB-AP for direct access to soc bus +target create ${_CHIPNAME}.ahb mem_ap -dap ${_CHIPNAME}.dap -ap-num 0 + +# default target is A55 core 0 +targets $_TARGETNAME.1 + --
