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"Antonio Borneo <[email protected]>" just uploaded a new patch set to 
Gerrit, which you can find at https://review.openocd.org/c/openocd/+/9165

-- gerrit

commit aa7f9fd53e088e04cdabba8c97eedcb43556dbe9
Author: Antonio Borneo <[email protected]>
Date:   Tue Oct 7 14:03:15 2025 +0200

    target: riscv: move the SMP commands under riscv
    
    For all the targets that support SMP, the sub-commands 'smp' and
    'smp_gdb' are under the arch name:
    - aarch64 smp
    - cortex_a smp
    - cortex_m smp
    - esp32 smp
    - mips_m4k smp
    
    Keep consistency among OpenOCD commands, and move under the arch
    name 'riscv' the SMP subcommands.
    
    Change-Id: Iede7841c2df8161ff2c6fea3be561d1f26ad6cd0
    Signed-off-by: Antonio Borneo <[email protected]>

diff --git a/doc/openocd.texi b/doc/openocd.texi
index a7c5d39d04..547e93b372 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -11825,16 +11825,16 @@ When utilizing version 0.11 of the RISC-V Debug 
Specification,
 and DBUS registers, respectively.
 @end deffn
 
-@deffn {Command} {smp} [on|off]
+@deffn {Command} {riscv smp} [on|off]
 Display, enable or disable SMP handling mode. This command is needed only if
 user wants to temporary @b{disable} SMP handling for an existing SMP group
 (see @code{aarch64 smp} for additional information). To define an SMP
 group the command @code{target smp} should be used.
 @end deffn
 
-@deffn {Command} {smp_gdb} [core_id]
+@deffn {Command} {riscv smp_gdb} [core_id]
 Display/set the current core displayed in GDB. This is needed only if
-@code{smp} was used.
+@code{riscv smp} was used.
 @end deffn
 
 @deffn {Config Command} {riscv use_bscan_tunnel} width [type]
diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c
index f8218af268..c606aa14ab 100644
--- a/src/target/riscv/riscv.c
+++ b/src/target/riscv/riscv.c
@@ -5849,6 +5849,9 @@ static const struct command_registration 
riscv_exec_command_handlers[] = {
                        "When off, users need to take care of memory coherency 
themselves, for example by using "
                        "`riscv exec_progbuf` to execute fence or CMO 
instructions."
        },
+       {
+               .chain = smp_command_handlers
+       },
        COMMAND_REGISTRATION_DONE
 };
 
@@ -5881,9 +5884,6 @@ static const struct command_registration 
riscv_command_handlers[] = {
                .usage = "",
                .chain = semihosting_common_handlers
        },
-       {
-               .chain = smp_command_handlers
-       },
        COMMAND_REGISTRATION_DONE
 };
 

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