This is an automated email from Gerrit. "Peter pan <[email protected]>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/9029
-- gerrit commit a08be36b05119929aabfe3718e26fbbb542757af Author: Jiafei Pan <[email protected]> Date: Mon Nov 3 16:10:37 2025 +0800 target: add NXP i.MX 91 and frdm-imx91 board support Add imx91 target and frdm-imx91 board file. Have verified with JLink: openocd -f interface/jlink.cfg -f board/nxp/frdm-imx91.cfg Change-Id: I15937febd4fb373f82a0597e08d34f25e799fc8e Signed-off-by: Jiafei Pan <[email protected]> diff --git a/tcl/board/nxp/frdm-imx91.cfg b/tcl/board/nxp/frdm-imx91.cfg new file mode 100644 index 0000000000..192975d62a --- /dev/null +++ b/tcl/board/nxp/frdm-imx91.cfg @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# configuration file for NXP frdm-imx91 +# + +transport select swd + +# default JTAG configuration has only SRST and no TRST +reset_config srst_only srst_push_pull + +# delay after SRST goes inactive +adapter srst delay 70 + + +# board has an i.MX91 with single Cortex-A55 core +set CHIPNAME imx91 +set CHIPCORES 1 + +# source SoC configuration +source [find target/nxp/imx91.cfg] diff --git a/tcl/target/nxp/imx91.cfg b/tcl/target/nxp/imx91.cfg new file mode 100644 index 0000000000..d5cb9ae273 --- /dev/null +++ b/tcl/target/nxp/imx91.cfg @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# configuration file for NXP i.MX91 family of SoCs +# +source [find target/swj-dp.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME imx91 +} + +# CoreSight Debug Access Port +if { [info exists DAP_TAPID] } { + set _DAP_TAPID $DAP_TAPID +} else { + set _DAP_TAPID 0x0892801d +} + +# the DAP tap +swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \ + -expected-id $_DAP_TAPID + +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +set _TARGETNAME $_CHIPNAME.a55 +set _CTINAME $_CHIPNAME.cti + +set DBGBASE {0x40810000 0x40910000} +set CTIBASE {0x40820000 0x40920000} + +cti create $_CTINAME.0 -dap $_CHIPNAME.dap -ap-num 1 \ + -baseaddr [lindex $CTIBASE 0] + +target create $_TARGETNAME.0 aarch64 -dap $_CHIPNAME.dap \ + -dbgbase [lindex $DBGBASE 0] -cti $_CTINAME.0 -coreid 0 + +# AHB-AP for direct access to soc bus +target create ${_CHIPNAME}.ahb mem_ap -dap ${_CHIPNAME}.dap -ap-num 0 + +targets $_TARGETNAME.0 --
