This is an automated email from Gerrit. "Antonio Borneo <[email protected]>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/9291
-- gerrit commit 608eabd8d134d18813e04fcee2868138e761de0d Author: Antonio Borneo <[email protected]> Date: Tue Dec 9 09:35:06 2025 +0100 target: cortex_a: support read and write watchpoints The current code for cortex_a watchpoint sets the field DBGWCR:LSC to '3', that corresponds to 'access' watchpoint. Thus, any 'r' or 'w' watchpoint is considered to 'a'. Convert the enum watchpoint_rw to the corresponding values for the field DBGWCR:LSC. Change-Id: Iccfddb3e34f3f26927983f3b00d9d5f81b06eb21 Signed-off-by: Antonio Borneo <[email protected]> diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c index 3d8603a4ba..2efbcce0c9 100644 --- a/src/target/cortex_a.c +++ b/src/target/cortex_a.c @@ -1769,7 +1769,6 @@ static int cortex_a_set_watchpoint(struct target *target, struct watchpoint *wat uint32_t address; uint8_t address_mask; uint8_t byte_address_select; - uint8_t load_store_access_control = 0x3; struct cortex_a_common *cortex_a = target_to_cortex_a(target); struct armv7a_common *armv7a = &cortex_a->armv7a_common; struct cortex_a_wrp *wrp_list = cortex_a->wrp_list; @@ -1827,6 +1826,22 @@ static int cortex_a_set_watchpoint(struct target *target, struct watchpoint *wat break; } + uint8_t load_store_access_control; + switch (watchpoint->rw) { + case WPT_READ: + load_store_access_control = 1; + break; + case WPT_WRITE: + load_store_access_control = 2; + break; + case WPT_ACCESS: + load_store_access_control = 3; + break; + default: + LOG_ERROR("BUG: watchpoint->rw neither read, write nor access"); + return ERROR_FAIL; + }; + watchpoint_set(watchpoint, wrp_i); control = (address_mask << 24) | (byte_address_select << 5) | --
