This is an automated email from Gerrit. "Tomas Vanek <[email protected]>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/9316
-- gerrit commit 9cbdb4fb33d53f9c014d80b679abc551ade9f3c8 Author: Tomas Vanek <[email protected]> Date: Fri Dec 12 18:26:04 2025 +0100 tcl/target/gd32vf103: adjust reset workaround to new riscv target Check if srst is configured. Avoid unnecessary double reset run if srst is configured. Write dmcontrol ackhavereset only if necessary. Add short delay to prevent strange 'Hart unexpectedly reset' and 'timed out while waiting for target halted' errors. Change-Id: I06b201bc5651c301912158c1436b9b3e3bc042a0 Signed-off-by: Tomas Vanek <[email protected]> diff --git a/tcl/target/gd32vf103.cfg b/tcl/target/gd32vf103.cfg index 026437b825..327733506f 100644 --- a/tcl/target/gd32vf103.cfg +++ b/tcl/target/gd32vf103.cfg @@ -69,21 +69,35 @@ $_TARGETNAME configure -event reset-assert { set dmcontrol_ackhavereset [expr {1 << 28}] set dmcontrol_haltreq [expr {1 << 31}] - global _RESETMODE - - # If hardware NRST signal is connected and configured (reset_config srst_only) - # the device has been recently reset in 'jtag arp_init-reset', therefore - # DM_DMSTATUS_ANYHAVERESET reads 1. - # The following 'halt' command checks this status bit - # and shows 'Hart 0 unexpectedly reset!' if set. - # Prevent this message by sending an acknowledge first. - set val [expr {$dmcontrol_dmactive | $dmcontrol_ackhavereset}] - riscv dmi_write $dmcontrol $val + set reset_config_options [reset_config] + set srst_is_configured [expr { + [string match {srst_only *} $reset_config_options] + || [string match {srst_and_trst *} $reset_config_options] + }] + # If hardware NRST signal is connected and configured + # (reset_config srst_only or srst_and_trst) + if {$srst_is_configured} { + if {$halt} { + # The device has been recently reset in 'jtag arp_init-reset', + # therefore DM_DMSTATUS_ANYHAVERESET reads 1. + # The following 'halt' command checks this status bit + # and shows 'Hart 0 unexpectedly reset!' if set. + # Prevent this message by sending an acknowledge first. + set val [expr {$dmcontrol_dmactive | $dmcontrol_ackhavereset}] + riscv dmi_write $dmcontrol $val + # Continue with the reset workaround to halt at flash start address + } else { + # Avoid the reset workaround at all. + return + } + } # Halt the core so that we can write to memory. We do this first so # that it doesn't clobber our dmcontrol configuration. halt + echo "gd32vf103 reset workaround" + # Set haltreq appropriately for the type of reset we're doing. This # replicates what the generic RISC-V reset_assert() function would # do if we weren't overriding it. The $_RESETMODE hack sucks, but @@ -114,6 +128,12 @@ $_TARGETNAME configure -event reset-assert { # Put the memory access mode back to what it was. default_mem_access + + # Short delay to prevent strange 'Hart unexpectedly reset' + # and 'timed out while waiting for target halted' errors + # caused probably by writing to dmcontrol in riscv_deassert_reset() + # too early after soft reset + sleep 10 } # On GD32VF103 the specification's requirement that each hart is in "exactly --
