This is an automated email from Gerrit. "Guillaume <[email protected]>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/9328
-- gerrit commit ff214e8f44f8eda8115ca4002e7f1eb1cc03fd31 Author: Guillaume Faussard <[email protected]> Date: Fri Dec 26 12:09:59 2025 +0100 tcl/target/stm32wba5x: Fix wrong addresses According to ST Reference Manual RM093 Rev 7: - OTP is 0x0BF90000 2.3.2 Memory map and register boundary addresses, page 84 - DBGMCU registers starts at 0xE0044000 43.5.1 System debug ROM table, page 1736 Change-Id: I735c6184d9f3fd767d9d776b238e88fcfbe8cc8d Signed-off-by: Guillaume Faussard <[email protected]> diff --git a/tcl/target/stm32wba5x.cfg b/tcl/target/stm32wba5x.cfg index cbbf99c338..9a6557c737 100644 --- a/tcl/target/stm32wba5x.cfg +++ b/tcl/target/stm32wba5x.cfg @@ -47,7 +47,7 @@ target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap -ap-num 1 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 flash bank $_CHIPNAME.flash stm32l4x 0x08000000 0 0 0 $_TARGETNAME -flash bank $_CHIPNAME.otp stm32l4x 0x0FF90000 0 0 0 $_TARGETNAME +flash bank $_CHIPNAME.otp stm32l4x 0x0bf90000 0 0 0 $_TARGETNAME # Common knowledges tells JTAG speed should be <= F_CPU/6. # F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on @@ -88,12 +88,12 @@ $_TARGETNAME configure -event reset-start { $_TARGETNAME configure -event examine-end { # Enable debug during low power modes (uses more power) - # DBGMCU_CR |= DBG_STANDBY | DBG_STOP - mmw 0xE0042004 0x00000006 0 + # DBGMCU_SCR |= DBG_STANDBY | DBG_STOP + mmw 0xE0044004 0x00000006 0 # Stop watchdog counters during halt # DBGMCU_APB1LFZR |= DBG_IWDG_STOP | DBG_WWDG_STOP - mmw 0xE0042008 0x00001800 0 + mmw 0xE0044008 0x00001800 0 } tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000 --
