This is an automated email from Gerrit. "Jérôme Pouiller <[email protected]>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/9452
-- gerrit commit a96acdae831b5eedceab66ffb108f7d706287b1d Author: Jérôme Pouiller <[email protected]> Date: Tue Feb 3 17:30:09 2026 +0100 tcl/target: Add support for Silabs Series 2 Add the required TCL file for Silabs Series-2. This file is inspired of efm32.cfg. For the consistency, this patch also introduce silabs/series0.cfg and silabs/series1.cfg. We keep efm32.cfg for the backward compatibility. Co-developed-by: Peter Johanson <[email protected]> Signed-off-by: Peter Johanson <[email protected]> Signed-off-by: Jérôme Pouiller <[email protected]> Change-Id: Ic923206617e5e5317bc68d9b5ccdd4604b7e72d7 diff --git a/tcl/target/efm32.cfg b/tcl/target/efm32.cfg index 2187c0aca4..fe793d0f59 100644 --- a/tcl/target/efm32.cfg +++ b/tcl/target/efm32.cfg @@ -1,55 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0-or-later +# SPDX-License-Identifier: BSD-3-Clause +# Copyright (c) 2026 Silicon Laboratories Inc. -# -# Silicon Labs (formerly Energy Micro) EFM32 target -# -# Note: All EFM32 chips have SWD support, but only newer series 1 -# chips have JTAG support. -# - -source [find target/swj-dp.tcl] - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME efm32 -} - -# Work-area is a space in RAM used for flash programming -# By default use 2kB -if { [info exists WORKAREASIZE] } { - set _WORKAREASIZE $WORKAREASIZE -} else { - set _WORKAREASIZE 0x800 -} - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - if { [using_jtag] } { - set _CPUTAPID 0x4ba00477 - } { - set _CPUTAPID 0x2ba01477 - } -} - -swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID -dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu - -adapter speed 1000 - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap - -$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 - -set _FLASHNAME $_CHIPNAME.flash -flash bank $_FLASHNAME efm32 0 0 0 0 $_TARGETNAME -flash bank userdata.flash efm32 0x0FE00000 0 0 0 $_TARGETNAME -flash bank lockbits.flash efm32 0x0FE04000 0 0 0 $_TARGETNAME - -if {![using_hla]} { - # if srst is not fitted use SYSRESETREQ to - # perform a soft reset - cortex_m reset_config sysresetreq -} +source [find target/silabs/series0.cfg] diff --git a/tcl/target/silabs/series0.cfg b/tcl/target/silabs/series0.cfg new file mode 100644 index 0000000000..2187c0aca4 --- /dev/null +++ b/tcl/target/silabs/series0.cfg @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Silicon Labs (formerly Energy Micro) EFM32 target +# +# Note: All EFM32 chips have SWD support, but only newer series 1 +# chips have JTAG support. +# + +source [find target/swj-dp.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME efm32 +} + +# Work-area is a space in RAM used for flash programming +# By default use 2kB +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x800 +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + if { [using_jtag] } { + set _CPUTAPID 0x4ba00477 + } { + set _CPUTAPID 0x2ba01477 + } +} + +swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +adapter speed 1000 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap + +$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME efm32 0 0 0 0 $_TARGETNAME +flash bank userdata.flash efm32 0x0FE00000 0 0 0 $_TARGETNAME +flash bank lockbits.flash efm32 0x0FE04000 0 0 0 $_TARGETNAME + +if {![using_hla]} { + # if srst is not fitted use SYSRESETREQ to + # perform a soft reset + cortex_m reset_config sysresetreq +} diff --git a/tcl/target/silabs/series1.cfg b/tcl/target/silabs/series1.cfg new file mode 100644 index 0000000000..fe793d0f59 --- /dev/null +++ b/tcl/target/silabs/series1.cfg @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright (c) 2026 Silicon Laboratories Inc. + +source [find target/silabs/series0.cfg] diff --git a/tcl/target/silabs/series2.cfg b/tcl/target/silabs/series2.cfg new file mode 100644 index 0000000000..aded5f62be --- /dev/null +++ b/tcl/target/silabs/series2.cfg @@ -0,0 +1,278 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright (c) 2026 Silicon Laboratories Inc. +# +# Silicon Labs Series 2 targets. These target are usually branded as EFM32PG2x +# or EFR32xG2x (eg. EFM32PG28, EFR32MG27, ...). +# +# Silicon Labs Series 0 and 1 are managed by efm32.cfg + +source [find target/swj-dp.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME efm32 +} + +# Work-area is a space in RAM used for flash programming. By default use 2kB +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x800 +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + # Cortex-M33 TAP IDs for Series 2 + if { [using_jtag] } { + set _CPUTAPID 0x6ba00477 + } { + set _CPUTAPID 0x6ba02477 + } +} + +# Family group xg21 and xg22 has flash base address 0x00000000. The others has +# flash base address 0x08000000 +if { [info exists FLASHBASE] } { + set _FLASHBASE $FLASHBASE +} else { + set _FLASHBASE 0x08000000 +} + +swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +adapter speed 1000 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +set _FLASHNAME $_CHIPNAME.flash + +flash bank $_FLASHNAME efm32 $_FLASHBASE 0 0 0 $_TARGETNAME +flash bank userdata.flash efm32 0x0FE00000 0 0 0 $_TARGETNAME + +if {![using_hla]} { + # if srst is not fitted use SYSRESETREQ to perform a soft reset + cortex_m reset_config sysresetreq + + $_TARGETNAME configure -event examine-fail silabs_s2_dci_read_se_status +} + +proc silabs_s2_dci_connect {} { + set target [target current] + set dap [$target cget -dap] + + # Read DP_IDCODE + set dp_id [$dap dpreg 0] + + if {$dp_id != 0x6BA02477} { + echo "Error: invalid DP ID for Silabs Series 2" + return + } + + poll off + + # Clear error and sticky flag conditions + # DP_ABORT = ORUNERRCLR | WDERRCLR STKERRCLR | STKCMPCLR + $dap dpreg 0 0x1E + + # DP_CTRL = CSYSPWRUPREQ | CDBGPWRUPREQ + $dap dpreg 0x04 0x50000000 + + # DP_SELECT for DCP AP register bank 0 + $dap dpreg 0x08 0x01000000 + + # Set CSW + $dap apreg 1 0x00 0x22000002 + + # Write AP_TAR = DCIID + $dap apreg 1 0x04 0x10FC + + # Read DP DRW + $dap dpreg 0x0C + + # Read AP RDBUFF + set DCIID [$dap apreg 1 0x0C] + if {$DCIID != 0xdc11d} { + echo "Failed to read correct DCIID" + } else { + echo "Successfully connected to DCI" + } +} + +proc silabs_s2_dci_read_status {} { + set target [target current] + set dap [$target cget -dap] + + # AP_TAR = DCISTATUS + $dap apreg 1 0x04 0x1008 + + set dcistatus [$dap apreg 1 0x0C] + set dcistatus [$dap dpreg 0x0C] + + return $dcistatus +} + +proc silabs_s2_dci_write_cmd { dci_write_word } { + set target [target current] + set dap [$target cget -dap] + + for {set i 0} {1} {incr i} { + if {$i >= 100} { + echo "$target DCI write timeout, unable to write command" + return + } + + set dcistatus [silabs_s2_dci_read_status] + if {$dcistatus & 1} { + echo "DCI WPENDING bit set, retrying" + sleep 10 + continue + } + + if {$dcistatus & 0x100} { + echo "DCI RDATAVALID is set, can't write to DCIWRITE" + return + } + + # AP_TAR = DCIWDATA + $dap apreg 1 0x04 0x1000 + + # Write word + $dap apreg 1 0x0C $dci_write_word + return + } +} + +proc silabs_s2_dci_read_response {} { + set target [target current] + set dap [$target cget -dap] + + for {set i 0} {1} {incr i} { + if {$i >= 100} { + echo "$target DCI read timeout" + return + } + + set dcistatus [silabs_s2_dci_read_status] + + if {$dcistatus & 0x100} { + # AP_TAR = DCIRDATA + $dap apreg 1 0x04 0x1004 + + set dciread [$dap apreg 1 0x0C] + set dciread [$dap dpreg 0x0C] + return $dciread + } else { + echo "DCI RDATAVALID is not set, retrying" + sleep 10 + continue + } + } +} + +proc silabs_s2_dci_device_erase {} { + silabs_s2_dci_connect + silabs_s2_dci_write_cmd 8 + silabs_s2_dci_write_cmd 0x430F0000 + + sleep 2000 + echo "Device erase command sent. Device should now be erased and debug should be available again after a reset" + poll on +} + +proc silabs_s2_dci_device_lock {} { + echo "Attempting to activate debug lock..." + silabs_s2_dci_connect + silabs_s2_dci_write_cmd 8 + silabs_s2_dci_write_cmd 0x430C0000 + + set recvlen [silabs_s2_dci_read_response] + + if {$recvlen & 0xFFFF0000} { + echo "command response was not OK, got $recvlen as command response. Can't continue." + poll on + return + } + + sleep 100 + + silabs_s2_dci_read_se_status + poll on +} + +proc silabs_s2_dci_read_se_status {} { + silabs_s2_dci_connect + + # Write len + silabs_s2_dci_write_cmd 8 + + # Write cmd + silabs_s2_dci_write_cmd 0xFE010000 + + set recvlen [silabs_s2_dci_read_response] + + if {$recvlen & 0xFFFF0000} { + echo "command response was not OK, got $recvlen as command response. Can't continue." + poll on + return + } + + set debuglock_idx 3 + + if {$recvlen == 0x28} { + set debuglock_idx 7 + } + + # decrement length word + set recvlen [expr {$recvlen - 4}] + + for {set i 0} {1} {incr i} { + if {$recvlen <= 0} { + break + } + + set recvlen [expr {$recvlen - 4}] + set sestatusarray($i) [silabs_s2_dci_read_response] + } + poll on + + echo "DCI SESTATUS response:" + set sestatusarray + + set debuglock $sestatusarray($debuglock_idx) + + if {$debuglock & 0x01} { + echo "Debug lock (config): Enabled" + } else { + echo "Debug lock (config): Disabled" + } + + if {$debuglock & 0x02} { + echo "Device erase: Enabled" + } else { + echo "Device erase: Disabled" + } + + if {$debuglock & 0x04} { + echo "Secure debug: Enabled" + } else { + echo "Secure debug: Disabled" + } + + if {$debuglock & 0x20} { + echo "Debug lock (hw status): Enabled" + echo "\n" + echo " * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *" + echo " You will not be able to communicate with this device" + echo " unless you perform a device erase (if available, indicated above)!" + echo " Try silabs_s2_dci_device_erase to attempt erase." + echo " * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *\n\n" + } else { + echo "Debug lock (hw status): Disabled" + } +} --
