This is an automated email from Gerrit. "Evgeniy Naydanov <[email protected]>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/9485
-- gerrit commit 8184f800d8da37c0b09b20696277137a63be7a72 Author: Evgeniy Naydanov <[email protected]> Date: Wed Feb 25 17:10:02 2026 +0300 poll targets in the end of `init` This allows to drop the call to respective poll implementations from `aarch64_examine()` and `cortex_a_init_debug_access()`, which in turn allows to drop the calls to `target_set_examined()`. However, after the patch the poll is not called at the end of `<target_name> arp_examine` for the following target types: * `aarch64` * `armv8r` * `cortex_a` * `cortex_r4` * `feroceon` This requires adjustment to config files (the list is the result of `git grep arp_examine -- tcl | cut -f1 -d: | sort -u`), except for (all files are in `tcl/target`): * `marvell/cn9130.cfg` -- `arp_examine` is in a comment. * `nrf52.cfg`, `nrf53.cfg`, `psoc4.cfg`, `psoc6.cfg` -- targets are `cortex_m`. * `nrf_common.cfg` -- used in `nrf91.cfg`, `nrf53.cfg`, still all targets are `cortex_m`. * `stm32mp13x.cfg` -- the call is in `reset-deassert-pre` event handler, `reset` polls at the end. * `stm32mp15x.cfg` -- for the calls in `reset-deassert-*` handlers the reason is the same, the call in `examine-end` handler is not affected since `$::CHIPNAME.cm4` is a `cortex_m` target. Change-Id: Ia038ed10b3862e7235b66bb6f42c2d3471c27d70 Signed-off-by: Evgeniy Naydanov <[email protected]> diff --git a/src/openocd.c b/src/openocd.c index f3e1bee48e..737e5cd518 100644 --- a/src/openocd.c +++ b/src/openocd.c @@ -175,6 +175,8 @@ COMMAND_HANDLER(handle_init_command) target_register_event_callback(log_target_callback_event_handler, CMD_CTX); + target_call_timer_callbacks_now(); + if (command_run_line(CMD_CTX, "_run_post_init_commands") != ERROR_OK) return ERROR_FAIL; diff --git a/src/target/aarch64.c b/src/target/aarch64.c index ed9cb48aa7..e5ba9dd164 100644 --- a/src/target/aarch64.c +++ b/src/target/aarch64.c @@ -2757,7 +2757,6 @@ static int aarch64_examine_first(struct target *target) target->state = TARGET_UNKNOWN; target->debug_reason = DBG_REASON_NOTHALTED; aarch64->isrmasking_mode = AARCH64_ISRMASK_ON; - target_set_examined(target); return ERROR_OK; } @@ -2773,9 +2772,6 @@ static int aarch64_examine(struct target *target) if (retval == ERROR_OK) retval = aarch64_init_debug_access(target); - if (retval == ERROR_OK) - retval = aarch64_poll(target); - return retval; } diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c index bc7550509c..1af75b4a5e 100644 --- a/src/target/cortex_a.c +++ b/src/target/cortex_a.c @@ -245,11 +245,7 @@ static int cortex_a_init_debug_access(struct target *target) return retval; retval = mem_ap_write_atomic_u32(armv7a->debug_ap, armv7a->debug_base + CPUDBG_DSCR, dscr | DSCR_HALT_DBG_MODE); - if (retval != ERROR_OK) - return retval; - - /* Since this is likely called from init or reset, update target state information*/ - return cortex_a_poll(target); + return retval; } static int cortex_a_wait_instrcmpl(struct target *target, uint32_t *dscr, bool force) @@ -3119,7 +3115,6 @@ static int cortex_a_examine_first(struct target *target) /* select debug_ap as default */ swjdp->apsel = armv7a->debug_ap->ap_num; - target_set_examined(target); return ERROR_OK; } diff --git a/tcl/board/lemaker_hikey.cfg b/tcl/board/lemaker_hikey.cfg index fc044359c1..9173977e73 100644 --- a/tcl/board/lemaker_hikey.cfg +++ b/tcl/board/lemaker_hikey.cfg @@ -20,6 +20,11 @@ proc core_up { args } { # examine remaining cores foreach _core $args { - ${_TARGETNAME}$_core arp_examine + set _current_target ${_TARGETNAME}$_core + $_current_target arp_examine + set _current_type [$_current_target cget -type] + if {$_current_type eq "aarch64" || $_current_type eq "cortex_a"} { + $_current_target arp_poll + } } } diff --git a/tcl/board/openrd.cfg b/tcl/board/openrd.cfg index f6c8317700..4e6948615c 100644 --- a/tcl/board/openrd.cfg +++ b/tcl/board/openrd.cfg @@ -29,6 +29,7 @@ proc openrd_init { } { # should then succeed. adapter assert srst feroceon.cpu arp_examine + feroceon.cpu arp_poll halt 0 adapter deassert srst wait_halt diff --git a/tcl/board/sheevaplug.cfg b/tcl/board/sheevaplug.cfg index 734fab6407..bcfca01acc 100644 --- a/tcl/board/sheevaplug.cfg +++ b/tcl/board/sheevaplug.cfg @@ -29,6 +29,7 @@ proc sheevaplug_init { } { # should then succeed. adapter assert srst feroceon.cpu arp_examine + feroceon.cpu arp_poll halt 0 adapter deassert srst wait_halt diff --git a/tcl/board/tocoding_poplar.cfg b/tcl/board/tocoding_poplar.cfg index 5f9dba43b0..e408f6e258 100644 --- a/tcl/board/tocoding_poplar.cfg +++ b/tcl/board/tocoding_poplar.cfg @@ -23,5 +23,6 @@ proc core_up { args } { # examine remaining cores foreach _core $args { ${_TARGETNAME}$_core arp_examine + ${_TARGETNAME}$_core arp_poll } } diff --git a/tcl/target/bluefield.cfg b/tcl/target/bluefield.cfg index 30ed527607..f3dfe2df4b 100644 --- a/tcl/target/bluefield.cfg +++ b/tcl/target/bluefield.cfg @@ -76,5 +76,6 @@ proc core_up { args } { # Examine remaining cores foreach _core $args { ${_TARGETNAME}$_core arp_examine + ${_TARGETNAME}$_core arp_poll } } diff --git a/tcl/target/ls1046a.cfg b/tcl/target/ls1046a.cfg index 3d96a994ed..e782c2a541 100644 --- a/tcl/target/ls1046a.cfg +++ b/tcl/target/ls1046a.cfg @@ -48,6 +48,7 @@ target create $_CHIPNAME.sap ls1_sap -chain-position $_CHIPNAME.sap -endian big proc core_up { args } { foreach core $args { $::_CHIPNAME.cpu$core arp_examine + $::_CHIPNAME.cpu$core arp_poll } } diff --git a/tcl/target/ti_k3.cfg b/tcl/target/ti_k3.cfg index 0dee74e5ee..c689aa81fc 100644 --- a/tcl/target/ti_k3.cfg +++ b/tcl/target/ti_k3.cfg @@ -406,12 +406,16 @@ proc _cpu_no_smp_up {} { $_current_target arp_examine $_current_target $_current_type dbginit + set _current_type [$_current_target cget -type] + if {$_current_type eq "aarch64" || $_current_type eq "cortex_r4"} { + $_current_target arp_poll + } } proc _armv8_smp_up {} { for { set _core 0 } { $_core < $::_armv8_cores } { incr _core } { $::_TARGETNAME.$::_armv8_cpu_name.$_core arp_examine - $::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 dbginit + $::_TARGETNAME.$::_armv8_cpu_name.$_core arp_poll $::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 smp on } # Set Default target as core 0 diff --git a/tcl/target/u8500.cfg b/tcl/target/u8500.cfg index ea3c7218ee..fc4231bf4d 100644 --- a/tcl/target/u8500.cfg +++ b/tcl/target/u8500.cfg @@ -133,12 +133,14 @@ proc enable_apetap {} { set status [$_TARGETNAME_1 curstate] if {[string equal "unknown" $status]} { $_TARGETNAME_1 arp_examine + $_TARGETNAME_1 arp_poll cache l2x conf 0xa0412000 8 } set status [$_TARGETNAME_2 curstate] if {[string equal "unknown" $status]} { $_TARGETNAME_2 arp_examine + $_TARGETNAME_2 arp_poll } } diff --git a/tcl/target/xilinx_zynqmp.cfg b/tcl/target/xilinx_zynqmp.cfg index e8224be043..c4e11309aa 100644 --- a/tcl/target/xilinx_zynqmp.cfg +++ b/tcl/target/xilinx_zynqmp.cfg @@ -102,6 +102,7 @@ proc core_up { args } { global _TARGETNAME foreach core $args { $_TARGETNAME.$core arp_examine + $_TARGETNAME.$core arp_poll } } --
