This is an automated email from Gerrit. "Florian Huehn <[email protected]>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/9731
-- gerrit commit 8deff89bfa642dbb0b928a92f4dd4ae4d09ba337 Author: Florian Huehn <[email protected]> Date: Fri Jun 5 14:31:19 2026 +0200 tcl/target: add support for NXP iMX95 Adds support for the NXP iMX95 target. Also adds support for the FTDI interface found on the Toradex Dahlia carrier board. Tested using the imx95 "Verdin" SoM on the Dahlia carrier baord. Change-Id: I8732d4964a653d6ee7cefb60e5e7251c58e060a8 Signed-off-by: Florian Huehn <[email protected]> diff --git a/tcl/board/toradex/dahlia-imx95.cfg b/tcl/board/toradex/dahlia-imx95.cfg new file mode 100644 index 0000000000..293689e731 --- /dev/null +++ b/tcl/board/toradex/dahlia-imx95.cfg @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Configuration file for the Toradex Dahlia base board +# with a Verdin IMX95 module inseted (IMX9596). +# +# Could specify external adpater by: +# openocd -f interface/jlink.cfg -f board/nxp/imx8ulp-evk.cfg +# otherwise use FTDI-based JTAG adapte by default. +# + +if { [adapter name] eq "undefined" } { + # Use on-board FTDI-based adapter + echo "Info: use FTDI adapter" + source [find interface/ftdi/toradex-dahlia.cfg] +} + +transport select jtag + +# Set a safe JTAG clock speed, can be overridden +adapter speed 1000 + +# The board has an i.MX95 with 6 Cortex-A55 cores +set CHIPNAME imx95 +set CHIPCORES 6 + +# Reset the entire board +# The iMX95 "Verdin" SoM doesn't connect the nTRST so we have to execute a full board reset +proc init_reset {mode} { + # Assert board reset + adapter assert trst + sleep 100 + + # Deassert board reset + adapter deassert trst + # Wait for the bootimage to finish memory initialisation + # Note: If you have U-Boot installed, set a sufficiently long delay before booting (ex. 10s) + sleep 7000 +} + +proc jtag_init {} { + init_reset startup +} + + +# Source SoC configuration +source [find target/nxp/imx95.cfg] diff --git a/tcl/interface/ftdi/toradex-dahlia.cfg b/tcl/interface/ftdi/toradex-dahlia.cfg new file mode 100644 index 0000000000..73689881e6 --- /dev/null +++ b/tcl/interface/ftdi/toradex-dahlia.cfg @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Configuration file for the Toradex Dahlia board +# + +adapter driver ftdi +ftdi vid_pid 0x0403 0x6011 +ftdi channel 1 + +ftdi layout_init 0x0098 0x009b +#MPSSE defaults to (TCK, TDI, TDO, TMS) on bits (0..3) +#ftdi_layout_signal TCK -data 0x01 -noe 0x01 +#ftdi_layout_signal TDI -data 0x02 -noe 0x02 +#ftdi_layout_signal TDO -input 0x04 +#ftdi_layout_signal TMS -data 0x08 -noe 0x08 +ftdi layout_signal nTRST -data 0x0010 +ftdi layout_signal LED -data 0x0080 + +reset_config trst_only trst_push_pull + +echo "Info: Using FTDI adapter. Make sure J6 is open." + diff --git a/tcl/target/nxp/imx95.cfg b/tcl/target/nxp/imx95.cfg new file mode 100644 index 0000000000..8a5a3a07ca --- /dev/null +++ b/tcl/target/nxp/imx95.cfg @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# configuration file for NXP i.MX95 family of SoCs +# +source [find target/swj-dp.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME imx95 +} + +if { [info exists CHIPCORES] } { + set _cores $CHIPCORES +} else { + set _cores 1 +} + +# CoreSight Debug Access Port +if { [info exists DAP_TAPID] } { + set _DAP_TAPID $DAP_TAPID +} else { + set _DAP_TAPID 0x8893801D +} + +# the DAP tap +swj_newdap $_CHIPNAME cpu -irlen 8 -ircapture 0x01 -irmask 0x0f \ + -expected-id $_DAP_TAPID + +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +set _TARGETNAME $_CHIPNAME.a55 +set _CTINAME $_CHIPNAME.cti + +set DBGBASE {0x40810000 0x40910000 0x40a10000 0x40b10000 0x40c10000 0x40d10000} +set CTIBASE {0x40820000 0x40920000 0x40a20000 0x40b20000 0x40c20000 0x40d20000} + +for { set _core 0 } { $_core < $_cores } { incr _core } { + + cti create $_CTINAME.$_core -dap $_CHIPNAME.dap -ap-num 1 \ + -baseaddr [lindex $CTIBASE $_core] + + target create $_TARGETNAME.$_core aarch64 -dap $_CHIPNAME.dap \ + -dbgbase [lindex $DBGBASE $_core] -cti $_CTINAME.$_core -coreid $_core +} + +# declare the auxiliary Cortex-M33 core on AP #3 +# note: could not test this +#target create ${_CHIPNAME}.m33 cortex_m -dap ${_CHIPNAME}.dap -ap-num 3 +# declare the auxiliary Cortex-M7 core on AP #? +# note: I don't know which AP it is on. + +# AHB-AP for direct access to soc bus +target create ${_CHIPNAME}.ahb mem_ap -dap ${_CHIPNAME}.dap -ap-num 1 + +# default target is A55 core 0 +targets $_TARGETNAME.0 --
