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-- gerrit commit 38c2d444068855f56c60f856d68d0a8330081bf3 Author: Konrad Dybcio <[email protected]> Date: Tue Jul 7 10:00:59 2026 +0200 tcl/target/qualcomm: Add Agatti platform The Qualcom Agatti platform (e.g. QRB2210, QCM2290) is an entry-level SoC featuring a 4xA53 cluster, and a couple of remote processors. Describe the SWD mappings from Application Processor's point of view. Change-Id: I64eeda250d900376bad444a660fdcb482b331227 Signed-off-by: Konrad Dybcio <[email protected]> diff --git a/tcl/target/qualcomm/agatti.cfg b/tcl/target/qualcomm/agatti.cfg new file mode 100644 index 0000000000..6496695324 --- /dev/null +++ b/tcl/target/qualcomm/agatti.cfg @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Configuration for the Qualcomm Agatti platform (e.g. QRB2210, QCM2290) + +source [find target/swj-dp.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME AGATTI +} + +set _CPU0_DBG_BASEADDR 0x09010000 +set _CPU1_DBG_BASEADDR 0x09110000 +set _CPU2_DBG_BASEADDR 0x09210000 +set _CPU3_DBG_BASEADDR 0x09310000 + +set _CTI0_BASEADDR 0x09020000 +set _CTI1_BASEADDR 0x09120000 +set _CTI2_BASEADDR 0x09220000 +set _CTI3_BASEADDR 0x09320000 + +source [find target/qualcomm/common.cfg] + +target smp \ + $_CHIPNAME.cpu0 \ + $_CHIPNAME.cpu1 \ + $_CHIPNAME.cpu2 \ + $_CHIPNAME.cpu3 diff --git a/tcl/target/qualcomm/common.cfg b/tcl/target/qualcomm/common.cfg new file mode 100644 index 0000000000..e114f1ed43 --- /dev/null +++ b/tcl/target/qualcomm/common.cfg @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Common configuration for most Qualcomm arm64 SoCs + +source [find target/swj-dp.tcl] + +if { ![info exists _CHIPNAME] } { + if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME + } else { + set _CHIPNAME FIXME_CHIPNAME + } +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +adapter speed 7500 +reset_config trst_and_srst + +# Set CUP TAP ID based on protocol selection +if { [using_jtag] } { + set _CPUTAPID 0x5ba00477 +} else { + set _CPUTAPID 0x5ba02477 +} + +swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID -irlen 4 + +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu -ignore-syspwrupack + +# AHB +target create ${_CHIPNAME}.axi mem_ap -dap ${_CHIPNAME}.dap -ap-num 0 +# APB +target create ${_CHIPNAME}.apb mem_ap -dap ${_CHIPNAME}.dap -ap-num 1 + +if { ![info exists _CTI0_BASEADDR] && [info exists _CTI_BASEADDR] } { + set _CTI0_BASEADDR $_CTI_BASEADDR +} + +for { set _core 0 } { $_core < 4 } { incr _core } { + if { ![info exists _CPU${_core}_DBG_BASEADDR] } { + continue + } + if { ![info exists _CTI${_core}_BASEADDR] } { + continue + } + + set _TARGETNAME $_CHIPNAME.cpu$_core + set _CTINAME $_CHIPNAME.cti$_core + set _DBG_BASEADDR [set _CPU${_core}_DBG_BASEADDR] + set _CTI_BASEADDR [set _CTI${_core}_BASEADDR] + + cti create $_CTINAME -dap $_CHIPNAME.dap -baseaddr $_CTI_BASEADDR -ap-num 1 + + if { $_core == 0 } { + target create $_TARGETNAME aarch64 -endian $_ENDIAN -dap $_CHIPNAME.dap -coreid $_core \ + -ap-num 1 \ + -cti $_CTINAME \ + -dbgbase $_DBG_BASEADDR \ + -event reset-assert-post { dap init } + $_TARGETNAME configure -event examine-end "$_TARGETNAME arp_halt; $_TARGETNAME arp_waitstate halted 1000" + } else { + target create $_TARGETNAME aarch64 -endian $_ENDIAN -dap $_CHIPNAME.dap -coreid $_core \ + -ap-num 1 \ + -cti $_CTINAME \ + -dbgbase $_DBG_BASEADDR \ + -defer-examine + } +} + +# Default breakpoints to hardware breakpoints +gdb breakpoint_override hard diff --git a/tcl/target/qualcomm/qcs6490.cfg b/tcl/target/qualcomm/qcs6490.cfg index d12708c8a2..52537b3ace 100644 --- a/tcl/target/qualcomm/qcs6490.cfg +++ b/tcl/target/qualcomm/qcs6490.cfg @@ -15,34 +15,7 @@ if { [info exists CHIPNAME] } { set _CHIPNAME QCS6490 } -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - set _ENDIAN little -} - -adapter speed 500 -reset_config trst_and_srst - -# Set CUP TAP ID based on protocol selection -if { [using_jtag] } { - set _CPUTAPID 0x5ba00477 -} else { - set _CPUTAPID 0x5ba02477 -} - -swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID -irlen 4 - -dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu -ignore-syspwrupack - -cti create $_CHIPNAME.cti -dap $_CHIPNAME.dap -baseaddr 0x87020000 -ap-num 1 - -target create $_CHIPNAME.cpu0 aarch64 -endian $_ENDIAN -dap $_CHIPNAME.dap -coreid 0 \ - -dbgbase 0x87010000 -cti $_CHIPNAME.cti -event reset-assert-post { dap init } - -$_CHIPNAME.cpu0 configure -event examine-end { - eval $_CHIPNAME.cpu0 arp_halt -} +set _CTI_BASEADDR 0x87020000 +set _CPU0_DBG_BASEADDR 0x87010000 -# Default breakpoints to hardware breakpoints -gdb_breakpoint_override hard +source [find target/qualcomm/common.cfg] --
