This is an automated email from Gerrit. "Ahmed Haoues <[email protected]>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/9699
-- gerrit commit 970ed9c90af75d30c114be7eeb4655edcc83753a Author: HAOUES Ahmed <[email protected]> Date: Thu Feb 19 12:24:51 2026 +0100 tcl/target: Add STM32C5x support Add configuration file for STM32C5 Change-Id: I7f1b1a2b2e536578bb9068e5f65abf812583373d Signed-off-by: HAOUES Ahmed <[email protected]> diff --git a/tcl/target/stm32c5x.cfg b/tcl/target/stm32c5x.cfg new file mode 100644 index 0000000000..49624c9c28 --- /dev/null +++ b/tcl/target/stm32c5x.cfg @@ -0,0 +1,178 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Configuration file for STM32C5x series. +# stm32c5x devices support both JTAG and SWD transports. + +source [find target/swj-dp.tcl] +source [find mem_helper.tcl] +source [find tools/stldr_helper.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME stm32c5x +} + +# Work-area is a space in RAM used for flash programming +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x8000 +} + +#jtag scan chain +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + if { [using_jtag] } { + set _CPUTAPID 0x6ba00477 + } { + set _CPUTAPID 0x6ba02477 + } +} + +set _ENDIAN little + +swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +if {[using_jtag]} { + jtag newtap $_CHIPNAME bs -irlen 5 +} + +target create $_CHIPNAME.ap0 mem_ap -endian $_ENDIAN -dap $_CHIPNAME.dap -ap-num 0 +target create $_CHIPNAME.cpu cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap -ap-num 1 + +$_CHIPNAME.cpu configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +flash bank $_CHIPNAME.flash stldr 0x08000000 0 16 0 [target current] + +# Common knowledge tells JTAG speed should be <= F_CPU/6. +# F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on +# the safe side. +# +# Note that there is a pretty wide band where things are +# more or less stable, see http://review.openocd.org/3366 +adapter speed 500 + +adapter srst delay 100 +if {[using_jtag]} { + jtag_ntrst_delay 100 +} + +if {[using_hla]} { + echo "Error : The selected adapter does not support debugging this device" + shutdown +} else { + # if srst is not fitted use SYSRESETREQ to + # perform a soft reset + cortex_m reset_config sysresetreq +} + +# get _CHIPNAME from current target +proc stm32c5x_get_chipname {} { + set t [target current] + set sep [string last "." $t] + if {$sep == -1} { + return $t + } + return [string range $t 0 [expr {$sep - 1}]] +} + +# like mrw, but with target selection +proc stm32c5x_mrw {used_target reg} { + return [$used_target read_memory $reg 32 1] +} + +# like mmw, but with target selection +proc stm32c5x_mmw {used_target reg setbits clearbits} { + set old [stm32c5x_mrw $used_target $reg] + set new [expr {($old & ~$clearbits) | $setbits}] + $used_target mww $reg $new +} + +# mmw for dbgmcu component registers, it accepts the register offset from dbgmcu base +proc stm32c5x_dbgmcu_mmw {reg_offset setbits clearbits} { + set _CHIPNAME [stm32c5x_get_chipname] + set used_target $_CHIPNAME.ap0 + set reg_addr [expr {0xE00E4000 + $reg_offset}] + + stm32c5x_mmw $used_target $reg_addr $setbits $clearbits +} + +# Get flash size in bytes +proc stm32c5x_get_size { dev_id } { + array set die_max_flash_size { + 0x44E 0x200 + 0x44F 0x100 + 0x45A 0x400 + } + + set flash_size [mrh 0x08FFF80C] + + if {$flash_size == 0x0000 || $flash_size == 0xFFFF } { + if {[info exists die_max_flash_size($dev_id)]} { + return [expr {$die_max_flash_size($dev_id) * 1024}] + } else { + echo "Error : No die $dev_id exists into die_max_flash_size array" + shutdown + } + } + return [expr {$flash_size * 1024}] +} + +# Set DEV_ID loader_file/link +# 0x44E "/path/to/STM32C5\[56\]x.xldr" +# or +# 0x44E "https://......./STM32C5\[56\]x.xldr"; +array set dev_id_loader { + 0x44E "https://github.com/STMicroelectronics/stm32c5xx-dfp/raw/a5f65bc64535cfa723e9d25f58d7ce23d0937aed/Flash/STM32C5%5B56%5Dx.xldr"; + 0x44F "https://github.com/STMicroelectronics/stm32c5xx-dfp/raw/a5f65bc64535cfa723e9d25f58d7ce23d0937aed/Flash/STM32C5%5B34%5Dx.xldr"; + 0x45A "https://github.com/STMicroelectronics/stm32c5xx-dfp/raw/a5f65bc64535cfa723e9d25f58d7ce23d0937aed/Flash/STM32C5%5B9A%5Dx.xldr"; +} + +set EXAMINED 0 + +$_CHIPNAME.cpu configure -event examine-end { + global EXAMINED + # Enable debug during low power modes (uses more power) + # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP + stm32c5x_dbgmcu_mmw 0x4 0x00000007 0 + + # Stop watchdog counters during halt + # DBGMCU_APB1LFZR |= DBG_IWDG_STOP | DBG_WWDG_STOP + stm32c5x_dbgmcu_mmw 0x8 0x00001800 0 + + if { $EXAMINED == 0 } { + # Read DBGMCU ID code and get device identification in hexadecimal + # dev_id = DBGMCU_IDCODE[0..11] + set dev_id [format 0x%03X [expr {([stm32c5x_mrw $_CHIPNAME.ap0 0XE00E4000] & 0xFFF)}]] + + set flash_size [stm32c5x_get_size $dev_id] + set flash_list [flash list] + if {[info exists dev_id_loader($dev_id)]} { + if {[file exists $dev_id_loader($dev_id)]} { + set loader_file $dev_id_loader($dev_id) + } else { + set loader_file [download_loader $dev_id_loader($dev_id)] + } + + for {set i 0} {$i < [llength $flash_list]} {incr i} { + set bank_desc [lindex $flash_list $i] + set bank_name [dict get $bank_desc name] + set bank_driver [dict get $bank_desc driver] + set bank_target [dict get $bank_desc target] + if {[string match "$_CHIPNAME.flash*" $bank_name] && + $bank_driver == "stldr" && + $bank_target == "$_CHIPNAME.cpu"} { + stldr set_loader $i $loader_file + stldr set_size $i $flash_size + } + } + } else { + echo "Error : No STLDR loader file found for device ID $dev_id" + echo "Error : Please check the 'dev_id_loader' table and set the correct loader file path for this device." + } + set EXAMINED 1 + } +} --
