This is an automated email from Gerrit. "liangzhen <[email protected]>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/9790
-- gerrit commit bd16b49ee0b3ffdc27c8e9a06f26d1f5b1b0af76 Author: Zane Leung <[email protected]> Date: Wed Jul 22 19:14:05 2026 +0800 target/riscv: implement soft_reset_halt using hartreset Add riscv_soft_reset_halt() which resets and halts only the current hart by temporarily forcing hartreset config, regardless of the global reset_config setting. This avoids issuing an ndmreset (full platform reset) when only a single hart needs to be reset and halted. Change-Id: Ic99cabb70038d9eb02b8a4da8e3244ee20ccc3c1 Signed-off-by: Zane Leung <[email protected]> diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c index d46f803cd7..fc5e6eb63e 100644 --- a/src/target/riscv/riscv.c +++ b/src/target/riscv/riscv.c @@ -2798,6 +2798,25 @@ static int riscv_deassert_reset(struct target *target) return tt->deassert_reset(target); } +static int riscv_soft_reset_halt(struct target *target) +{ + LOG_TARGET_DEBUG(target, ""); + struct target_type *tt = get_target_type(target); + if (!tt) + return ERROR_FAIL; + + target->reset_halt = true; + enum riscv_reset_config config = reset_config; + reset_config = RISCV_RESET_CONFIG_HARTRESET; + + int retval = tt->assert_reset(target); + reset_config = config; + if (retval != ERROR_OK) + return retval; + + return tt->deassert_reset(target); +} + /* "wp_is_set" array must have at least "r->trigger_count" items. */ static int disable_watchpoints(struct target *target, bool *wp_is_set) { @@ -6014,6 +6033,7 @@ struct target_type riscv_target = { .assert_reset = riscv_assert_reset, .deassert_reset = riscv_deassert_reset, + .soft_reset_halt = riscv_soft_reset_halt, .read_memory = riscv_read_memory, .write_memory = riscv_write_memory, --
