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"Jerry Zhang Jian <[email protected]>" just uploaded a new patch set 
to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/9804

-- gerrit

commit b0732668e3dc32c25fc7f7452823497acfbcca3a
Author: Jerry Zhang Jian <[email protected]>
Date:   Tue Jul 21 15:33:01 2026 +0800

    target/riscv: add Smcsrind/Sscsrind alias CSRs
    
    Add the remaining indirect CSR aliases sireg2-6, mireg2-6, and
    vsireg2-6. The select and primary alias CSRs were already present.
    
    Change-Id: I7e0affaefa42aa95c927ae9685b2e8e5e22abd1e
    Signed-off-by: Jerry Zhang Jian <[email protected]>

diff --git a/src/target/riscv/encoding.h b/src/target/riscv/encoding.h
index a1829fc5c1..2f91b57716 100644
--- a/src/target/riscv/encoding.h
+++ b/src/target/riscv/encoding.h
@@ -2851,6 +2851,11 @@
 #define CSR_SCTRSTATUS 0x14f
 #define CSR_SISELECT 0x150
 #define CSR_SIREG 0x151
+#define CSR_SIREG2 0x152
+#define CSR_SIREG3 0x153
+#define CSR_SIREG4 0x155
+#define CSR_SIREG5 0x156
+#define CSR_SIREG6 0x157
 #define CSR_STOPEI 0x15c
 #define CSR_SCTRDEPTH 0x15f
 #define CSR_SATP 0x180
@@ -2867,6 +2872,11 @@
 #define CSR_VSCTRCTL 0x24e
 #define CSR_VSISELECT 0x250
 #define CSR_VSIREG 0x251
+#define CSR_VSIREG2 0x252
+#define CSR_VSIREG3 0x253
+#define CSR_VSIREG4 0x255
+#define CSR_VSIREG5 0x256
+#define CSR_VSIREG6 0x257
 #define CSR_VSTOPEI 0x25c
 #define CSR_VSATP 0x280
 #define CSR_HSTATUS 0x600
@@ -2935,6 +2945,11 @@
 #define CSR_MCTRCTL 0x34e
 #define CSR_MISELECT 0x350
 #define CSR_MIREG 0x351
+#define CSR_MIREG2 0x352
+#define CSR_MIREG3 0x353
+#define CSR_MIREG4 0x355
+#define CSR_MIREG5 0x356
+#define CSR_MIREG6 0x357
 #define CSR_MTOPEI 0x35c
 #define CSR_PMPCFG0 0x3a0
 #define CSR_PMPCFG1 0x3a1
@@ -4613,6 +4628,11 @@ DECLARE_CSR(sctrctl, CSR_SCTRCTL)
 DECLARE_CSR(sctrstatus, CSR_SCTRSTATUS)
 DECLARE_CSR(siselect, CSR_SISELECT)
 DECLARE_CSR(sireg, CSR_SIREG)
+DECLARE_CSR(sireg2, CSR_SIREG2)
+DECLARE_CSR(sireg3, CSR_SIREG3)
+DECLARE_CSR(sireg4, CSR_SIREG4)
+DECLARE_CSR(sireg5, CSR_SIREG5)
+DECLARE_CSR(sireg6, CSR_SIREG6)
 DECLARE_CSR(stopei, CSR_STOPEI)
 DECLARE_CSR(sctrdepth, CSR_SCTRDEPTH)
 DECLARE_CSR(satp, CSR_SATP)
@@ -4629,6 +4649,11 @@ DECLARE_CSR(vstimecmp, CSR_VSTIMECMP)
 DECLARE_CSR(vsctrctl, CSR_VSCTRCTL)
 DECLARE_CSR(vsiselect, CSR_VSISELECT)
 DECLARE_CSR(vsireg, CSR_VSIREG)
+DECLARE_CSR(vsireg2, CSR_VSIREG2)
+DECLARE_CSR(vsireg3, CSR_VSIREG3)
+DECLARE_CSR(vsireg4, CSR_VSIREG4)
+DECLARE_CSR(vsireg5, CSR_VSIREG5)
+DECLARE_CSR(vsireg6, CSR_VSIREG6)
 DECLARE_CSR(vstopei, CSR_VSTOPEI)
 DECLARE_CSR(vsatp, CSR_VSATP)
 DECLARE_CSR(hstatus, CSR_HSTATUS)
@@ -4697,6 +4722,11 @@ DECLARE_CSR(mtval2, CSR_MTVAL2)
 DECLARE_CSR(mctrctl, CSR_MCTRCTL)
 DECLARE_CSR(miselect, CSR_MISELECT)
 DECLARE_CSR(mireg, CSR_MIREG)
+DECLARE_CSR(mireg2, CSR_MIREG2)
+DECLARE_CSR(mireg3, CSR_MIREG3)
+DECLARE_CSR(mireg4, CSR_MIREG4)
+DECLARE_CSR(mireg5, CSR_MIREG5)
+DECLARE_CSR(mireg6, CSR_MIREG6)
 DECLARE_CSR(mtopei, CSR_MTOPEI)
 DECLARE_CSR(pmpcfg0, CSR_PMPCFG0)
 DECLARE_CSR(pmpcfg1, CSR_PMPCFG1)

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