Comments?
This moves handling of problems with resetting into the halted state
into the target implementation.
Also target_process_reset() is now simpler and has error handling,
e.g. if assert reset fails, then target_process_reset() will propagate
that error.
cmd_ctx was passed in to examine(), which is wrong - removed that.
--
Øyvind Harboe
http://www.zylin.com/zy1000.html
ARM7 ARM9 XScale Cortex
JTAG debugger and flash programmer
### Eclipse Workspace Patch 1.0
#P openocd
Index: src/target/arm11.h
===================================================================
--- src/target/arm11.h (revision 876)
+++ src/target/arm11.h (working copy)
@@ -188,7 +188,7 @@
int arm11_halt(struct target_s *target);
int arm11_resume(struct target_s *target, int current, u32 address, int
handle_breakpoints, int debug_execution);
int arm11_step(struct target_s *target, int current, u32 address, int
handle_breakpoints);
-int arm11_examine(struct command_context_s *cmd_ctx, struct target_s *target);
+int arm11_examine(struct target_s *target);
/* target reset control */
int arm11_assert_reset(struct target_s *target);
Index: src/target/arm7tdmi.h
===================================================================
--- src/target/arm7tdmi.h (revision 876)
+++ src/target/arm7tdmi.h (working copy)
@@ -40,7 +40,7 @@
int arm7tdmi_register_commands(struct command_context_s *cmd_ctx);
int arm7tdmi_init_arch_info(target_t *target, arm7tdmi_common_t *arm7tdmi, int
chain_pos, char *variant);
int arm7tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s
*target);
-int arm7tdmi_examine(struct command_context_s *cmd_ctx, struct target_s
*target);
+int arm7tdmi_examine(struct target_s *target);
#endif /* ARM7TDMI_H */
Index: src/target/mips_m4k.c
===================================================================
--- src/target/mips_m4k.c (revision 876)
+++ src/target/mips_m4k.c (working copy)
@@ -46,7 +46,7 @@
int mips_m4k_quit();
int mips_m4k_target_command(struct command_context_s *cmd_ctx, char *cmd, char
**args, int argc, struct target_s *target);
-int mips_m4k_examine(struct command_context_s *cmd_ctx, struct target_s
*target);
+int mips_m4k_examine(struct target_s *target);
int mips_m4k_assert_reset(target_t *target);
int mips_m4k_deassert_reset(target_t *target);
@@ -610,7 +610,7 @@
return ERROR_OK;
}
-int mips_m4k_examine(struct command_context_s *cmd_ctx, struct target_s
*target)
+int mips_m4k_examine(struct target_s *target)
{
int retval;
mips32_common_t *mips32 = target->arch_info;
Index: src/target/arm7_9_common.c
===================================================================
--- src/target/arm7_9_common.c (revision 882)
+++ src/target/arm7_9_common.c (working copy)
@@ -821,12 +821,26 @@
int arm7_9_deassert_reset(target_t *target)
{
+ int retval=ERROR_OK;
LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
/* deassert reset lines */
jtag_add_reset(0, 0);
- return ERROR_OK;
+ if ((jtag_reset_config & RESET_SRST_PULLS_TRST)!=0)
+ {
+ /* set up embedded ice registers again */
+ if ((retval=target->type->examine(target))!=ERROR_OK)
+ return retval;
+
+ if (target->reset_halt)
+ {
+ /* halt the CPU as embedded ice was not set up in reset
*/
+ if ((retval=target->type->halt(target))!=ERROR_OK)
+ return retval;
+ }
+ }
+ return retval;
}
int arm7_9_clear_halt(target_t *target)
@@ -961,6 +975,12 @@
int arm7_9_halt(target_t *target)
{
+ if ((target->state==TARGET_RESET)&&((jtag_reset_config &
RESET_SRST_PULLS_TRST)!=0))
+ {
+ LOG_WARNING("arm7/9 can't halt a target in reset if srst pulls
trst - halting after reset");
+ return ERROR_OK;
+ }
+
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
Index: src/target/arm9tdmi.c
===================================================================
--- src/target/arm9tdmi.c (revision 876)
+++ src/target/arm9tdmi.c (working copy)
@@ -850,7 +850,7 @@
}
-int arm9tdmi_examine(struct command_context_s *cmd_ctx, struct target_s
*target)
+int arm9tdmi_examine(struct target_s *target)
{
/* get pointers to arch-specific information */
int retval;
Index: src/target/feroceon.c
===================================================================
--- src/target/feroceon.c (revision 876)
+++ src/target/feroceon.c (working copy)
@@ -54,7 +54,7 @@
#include <stdlib.h>
#include <string.h>
-int feroceon_examine(struct command_context_s *cmd_ctx, struct target_s
*target);
+int feroceon_examine(struct target_s *target);
int feroceon_target_command(struct command_context_s *cmd_ctx, char *cmd, char
**args, int argc, struct target_s *target);
int feroceon_bulk_write_memory(target_t *target, u32 address, u32 count, u8
*buffer);
int feroceon_init_target(struct command_context_s *cmd_ctx, struct target_s
*target);
@@ -694,13 +694,13 @@
}
-int feroceon_examine(struct command_context_s *cmd_ctx, struct target_s
*target)
+int feroceon_examine(struct target_s *target)
{
armv4_5_common_t *armv4_5;
arm7_9_common_t *arm7_9;
int retval;
- retval = arm9tdmi_examine(cmd_ctx, target);
+ retval = arm9tdmi_examine(target);
if (retval!=ERROR_OK)
return retval;
Index: src/target/target.c
===================================================================
--- src/target/target.c (revision 885)
+++ src/target/target.c (working copy)
@@ -290,7 +290,7 @@
*
* For the "reset halt/init" case we must only set up the registers
here.
*/
- if ((retval = target_examine(cmd_ctx)) != ERROR_OK)
+ if ((retval = target_examine()) != ERROR_OK)
return retval;
keep_alive(); /* we might be running on a very slow JTAG clk */
@@ -303,14 +303,10 @@
*/
target_free_all_working_areas_restore(target, 0);
target->reset_halt=((reset_mode==RESET_HALT)||(reset_mode==RESET_INIT));
- target->type->assert_reset(target);
+ if ((retval = target->type->assert_reset(target))!=ERROR_OK)
+ return retval;
target = target->next;
}
- if ((retval = jtag_execute_queue()) != ERROR_OK)
- {
- LOG_WARNING("JTAG communication failed asserting reset.");
- retval = ERROR_OK;
- }
/* request target halt if necessary, and schedule further action */
target = targets;
@@ -318,23 +314,24 @@
{
if (reset_mode!=RESET_RUN)
{
- if ((jtag_reset_config & RESET_SRST_PULLS_TRST)==0)
- target_halt(target);
+ if ((retval = target_halt(target))!=ERROR_OK)
+ return retval;
}
target = target->next;
}
- if ((retval = jtag_execute_queue()) != ERROR_OK)
+ target = targets;
+ while (target)
{
- LOG_WARNING("JTAG communication failed while reset was
asserted. Consider using srst_only for reset_config.");
- retval = ERROR_OK;
+ if ((retval = target->type->deassert_reset(target))!=ERROR_OK)
+ return retval;
+ target = target->next;
}
target = targets;
while (target)
{
- target->type->deassert_reset(target);
- /* We can fail to bring the target into the halted state */
+ /* We can fail to bring the target into the halted state, try
after reset has been deasserted */
if (target->reset_halt)
{
/* wait up to 1 second for halt. */
@@ -342,25 +339,14 @@
if (target->state != TARGET_HALTED)
{
LOG_WARNING("Failed to reset target into halted
mode - issuing halt");
- target->type->halt(target);
+ if ((retval =
target->type->halt(target))!=ERROR_OK)
+ return retval;
}
}
target = target->next;
}
- if ((retval = jtag_execute_queue()) != ERROR_OK)
- {
- LOG_WARNING("JTAG communication failed while deasserting
reset.");
- retval = ERROR_OK;
- }
-
- if (jtag_reset_config & RESET_SRST_PULLS_TRST)
- {
- /* If TRST was asserted we need to set up registers again */
- if ((retval = target_examine(cmd_ctx)) != ERROR_OK)
- return retval;
- }
LOG_DEBUG("Waiting for halted stated as appropriate");
@@ -397,7 +383,7 @@
return ERROR_OK;
}
-static int default_examine(struct command_context_s *cmd_ctx, struct target_s
*target)
+static int default_examine(struct target_s *target)
{
target->type->examined = 1;
return ERROR_OK;
@@ -415,7 +401,7 @@
target_t *target = targets;
while (target)
{
- if ((retval = target->type->examine(cmd_ctx, target))!=ERROR_OK)
+ if ((retval = target->type->examine(target))!=ERROR_OK)
return retval;
target = target->next;
}
Index: src/target/arm9tdmi.h
===================================================================
--- src/target/arm9tdmi.h (revision 876)
+++ src/target/arm9tdmi.h (working copy)
@@ -56,7 +56,7 @@
};
extern int arm9tdmi_init_target(struct command_context_s *cmd_ctx, struct
target_s *target);
-int arm9tdmi_examine(struct command_context_s *cmd_ctx, struct target_s
*target);
+int arm9tdmi_examine(struct target_s *target);
extern int arm9tdmi_init_arch_info(target_t *target, arm9tdmi_common_t
*arm9tdmi, int chain_pos, char *variant);
extern int arm9tdmi_register_commands(struct command_context_s *cmd_ctx);
Index: src/target/arm11.c
===================================================================
--- src/target/arm11.c (revision 876)
+++ src/target/arm11.c (working copy)
@@ -1378,7 +1378,7 @@
}
/* talk to the target and set things up */
-int arm11_examine(struct command_context_s *cmd_ctx, struct target_s *target)
+int arm11_examine(struct target_s *target)
{
FNC_INFO;
Index: src/target/target.h
===================================================================
--- src/target/target.h (revision 877)
+++ src/target/target.h (working copy)
@@ -182,7 +182,7 @@
*
* invoked every time after the jtag chain has been validated/examined
*/
- int (*examine)(struct command_context_s *cmd_ctx, struct target_s
*target);
+ int (*examine)(struct target_s *target);
/* Set up structures for target.
*
* It is illegal to talk to the target at this stage as this fn is
invoked
@@ -250,7 +250,7 @@
extern int target_register_commands(struct command_context_s *cmd_ctx);
extern int target_register_user_commands(struct command_context_s *cmd_ctx);
extern int target_init(struct command_context_s *cmd_ctx);
-extern int target_examine(struct command_context_s *cmd_ctx);
+extern int target_examine();
extern int handle_target(void *priv);
extern int target_process_reset(struct command_context_s *cmd_ctx, enum
target_reset_mode reset_mode);
Index: src/target/arm7tdmi.c
===================================================================
--- src/target/arm7tdmi.c (revision 876)
+++ src/target/arm7tdmi.c (working copy)
@@ -708,7 +708,7 @@
armv4_5->core_cache = (*cache_p);
}
-int arm7tdmi_examine(struct command_context_s *cmd_ctx, struct target_s
*target)
+int arm7tdmi_examine(struct target_s *target)
{
int retval;
armv4_5_common_t *armv4_5 = target->arch_info;
Index: src/target/cortex_m3.c
===================================================================
--- src/target/cortex_m3.c (revision 876)
+++ src/target/cortex_m3.c (working copy)
@@ -51,7 +51,7 @@
int cortex_m3_load_core_reg_u32(target_t *target, enum armv7m_regtype type,
u32 num, u32 *value);
int cortex_m3_store_core_reg_u32(target_t *target, enum armv7m_regtype type,
u32 num, u32 value);
int cortex_m3_target_request_data(target_t *target, u32 size, u8 *buffer);
-int cortex_m3_examine(struct command_context_s *cmd_ctx, struct target_s
*target);
+int cortex_m3_examine(struct target_s *target);
#ifdef ARMV7_GDB_HACKS
extern u8 armv7m_gdb_dummy_cpsr_value[];
@@ -1307,7 +1307,7 @@
return ERROR_OK;
}
-int cortex_m3_examine(struct command_context_s *cmd_ctx, struct target_s
*target)
+int cortex_m3_examine(struct target_s *target)
{
int retval;
u32 cpuid, fpcr, dwtcr, ictr;
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