the attached patch defines resetting the target into the halted or running
state as an atomic operation.
Previously this would be achived by issuing halt while reset was asserted.
Halt then needed to have conditional code, mostly to ignore what was already
done in assert reset.
Resetting into the halted state takes voodoo in assert+deassert reset.
Another issue not tackled yet is that assert/deassert reset was defined
as two different functions so as to allow multiple targets. However, with
the implementation of assert/deassert wiggling the reset lines directly,
that won't work. That cleanup is for another day.
Objections?
Comments?
--
Øyvind Harboe
http://www.zylin.com/zy1000.html
ARM7 ARM9 XScale Cortex
JTAG debugger and flash programmer
Index: C:/workspace/openocd/src/target/arm11.c
===================================================================
--- C:/workspace/openocd/src/target/arm11.c (revision 887)
+++ C:/workspace/openocd/src/target/arm11.c (working copy)
@@ -995,6 +995,13 @@
arm11->trst_active = true;
#endif
+ if (target->reset_halt)
+ {
+ int retval;
+ if ((retval = target_halt(target))!=ERROR_OK)
+ return retval;
+ }
+
return ERROR_OK;
}
Index: C:/workspace/openocd/src/target/arm7_9_common.c
===================================================================
--- C:/workspace/openocd/src/target/arm7_9_common.c (revision 887)
+++ C:/workspace/openocd/src/target/arm7_9_common.c (working copy)
@@ -815,6 +815,14 @@
armv4_5_invalidate_core_regs(target);
+ if (target->reset_halt)
+ {
+ int retval;
+ if ((retval = target_halt(target))!=ERROR_OK)
+ return retval;
+ }
+
+
return ERROR_OK;
}
Index: C:/workspace/openocd/src/target/cortex_m3.c
===================================================================
--- C:/workspace/openocd/src/target/cortex_m3.c (revision 887)
+++ C:/workspace/openocd/src/target/cortex_m3.c (working copy)
@@ -762,6 +762,13 @@
armv7m_invalidate_core_regs(target);
+ if (target->reset_halt)
+ {
+ int retval;
+ if ((retval = target_halt(target))!=ERROR_OK)
+ return retval;
+ }
+
return ERROR_OK;
}
Index: C:/workspace/openocd/src/target/mips_m4k.c
===================================================================
--- C:/workspace/openocd/src/target/mips_m4k.c (revision 887)
+++ C:/workspace/openocd/src/target/mips_m4k.c (working copy)
@@ -266,6 +266,14 @@
mips32_invalidate_core_regs(target);
+ if (target->reset_halt)
+ {
+ int retval;
+ if ((retval = target_halt(target))!=ERROR_OK)
+ return retval;
+ }
+
+
return ERROR_OK;
}
Index: C:/workspace/openocd/src/target/target.c
===================================================================
--- C:/workspace/openocd/src/target/target.c (revision 887)
+++ C:/workspace/openocd/src/target/target.c (working copy)
@@ -308,18 +308,6 @@
target = target->next;
}
- /* request target halt if necessary, and schedule further action */
- target = targets;
- while (target)
- {
- if (reset_mode!=RESET_RUN)
- {
- if ((retval = target_halt(target))!=ERROR_OK)
- return retval;
- }
- target = target->next;
- }
-
target = targets;
while (target)
{
Index: C:/workspace/openocd/src/target/xscale.c
===================================================================
--- C:/workspace/openocd/src/target/xscale.c (revision 887)
+++ C:/workspace/openocd/src/target/xscale.c (working copy)
@@ -1579,6 +1579,13 @@
jtag_execute_queue();
target->state = TARGET_RESET;
+
+ if (target->reset_halt)
+ {
+ int retval;
+ if ((retval = target_halt(target))!=ERROR_OK)
+ return retval;
+ }
return ERROR_OK;
}
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