On Mon, 6 Oct 2008, Magnus Lundin wrote: > Hi > > I am just guessing here but it can an issue with the timing of the AHB > bus and running from flash at 50MHz. > The SWLDP overrun is received through the JTAG interface, so it seems > JTAG is working. > SWDLP overruns are not JTAG problems, they are when the debug unit on th > CM3 receives > debug commands faster than it can process them. > > The overrun errors typically occurs when OpenOCD tries to access memory > mapped debug registers while the processor > is running. Then the running processor and the debug unit are contending > for the AHB bus. > > As I can understand things, when the processor is halted then OpenOcd > can write to flash memory. > Can the processor be single stepped ?
In case I have described, answer to this question is no. > Can you put a breakpoint after the pll setting code and run to the > breakpoint and then talk to the processor with OpenOCD ? Similarly, no. OpenOCD is not able to reset uC. What I do in this case is pushing a board reset button, then connect to the openocd server via telnet, and give the following commands: init and halt. After that it is posible to load and debug program or erase flash. Next time, when OpenOCD try force reset and init uC, whole problem start agian. Maybe there is a better way to solve this problem? Why when I debug a program in RAM (in flash I have the program that work with slow clock) and that program set the PLL frequency to 50MHz, the openocd work fine? -- Mariusz _______________________________________________ Openocd-development mailing list [email protected] https://lists.berlios.de/mailman/listinfo/openocd-development
