Hi, I've got an ARM926EJ-S target with an SPI flash (4 x ST Micro m25p32) attached to a Flash Interface Unit (FIU) controller. I don't see any way to configure this in OpenOCD so I presume SPI flash is not supported.
Could anyone give me a high level description on what would be needed to add this support and how it should be integrated into OpenOCD? The flash itself uses byte writes to initiate program/erase/status cycles just like an 8bit parallel flash (though I don't recognize the command set) and includes a CFI info query command as well. The FIU on the ARM926EJ-S maps the SPI flash to the ARM address space starting at address 0x40000000 so it reads like ordinary memory. I'm not sure what it does for writes to that space but the FIU contains a set of registers (the UMA) to allow write transactions and I think this is the preferred write mechanism (I just had a quick look at the datasheet so I could have this wrong). Is this a common way to interface SPI flash to a processor? Is it in any way standard on ARM (I can't find any reference to it in the ARM9E or ARM926 docs so I think not)? So it looks to me like there could be a generic SPI flash writing part and a target specific FIU part required to support this device. Is this true of other targets that support SPI flash? What is the preferred way to handle this in OpenOCD? Thanks, John McCarthy. _______________________________________________ Openocd-development mailing list [email protected] https://lists.berlios.de/mailman/listinfo/openocd-development
