Index: src/target/arm720t.c
===================================================================
--- src/target/arm720t.c	(revision 1229)
+++ src/target/arm720t.c	(working copy)
@@ -456,12 +456,12 @@
 	return ERROR_OK;
 }
 
-int arm720t_init_arch_info(target_t *target, arm720t_common_t *arm720t, jtag_tap_t *tap, const char *variant)
+int arm720t_init_arch_info(target_t *target, arm720t_common_t *arm720t, jtag_tap_t *tap)
 {
 	arm7tdmi_common_t *arm7tdmi = &arm720t->arm7tdmi_common;
 	arm7_9_common_t *arm7_9 = &arm7tdmi->arm7_9_common;
 	
-	arm7tdmi_init_arch_info(target, arm7tdmi, tap, variant);
+	arm7tdmi_init_arch_info(target, arm7tdmi, tap);
 
 	arm7tdmi->arch_info = arm720t;
 	arm720t->common_magic = ARM720T_COMMON_MAGIC;
@@ -485,7 +485,7 @@
 {
 	arm720t_common_t *arm720t = calloc(1,sizeof(arm720t_common_t));
 	
-	arm720t_init_arch_info(target, arm720t, target->tap, target->variant);
+	arm720t_init_arch_info(target, arm720t, target->tap);
 
 	return ERROR_OK;
 }
Index: src/target/arm7tdmi.c
===================================================================
--- src/target/arm7tdmi.c	(revision 1229)
+++ src/target/arm7tdmi.c	(working copy)
@@ -364,7 +364,6 @@
 	 * reading PC in Thumb state gives address of instruction + 4
 	 */
 	*pc -= 0xa;
-	
 }
 
 void arm7tdmi_read_core_regs(target_t *target, u32 mask, u32* core_regs[16])
@@ -391,7 +390,6 @@
 			/* nothing fetched, STM still in EXECUTE (1+i cycle) */
 			arm7tdmi_clock_data_in(jtag_info, core_regs[i]);
 	}
-
 }
 
 void arm7tdmi_read_core_regs_target_buffer(target_t *target, u32 mask, void* buffer, int size)
@@ -435,7 +433,6 @@
 			}
 		}
 	}
-	
 }
 
 void arm7tdmi_read_xpsr(target_t *target, u32 *xpsr, int spsr)
@@ -456,7 +453,6 @@
 	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 	/* nothing fetched, STR still in EXECUTE (2nd cycle) */
 	arm7tdmi_clock_data_in(jtag_info, xpsr);
-
 }
 
 void arm7tdmi_write_xpsr(target_t *target, u32 xpsr, int spsr)
@@ -507,7 +503,6 @@
 	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 	/* nothing fetched, MSR in EXECUTE (2) */
 	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
-	
 }
 
 void arm7tdmi_write_core_regs(target_t *target, u32 mask, u32 core_regs[16])
@@ -535,7 +530,6 @@
 			arm7tdmi_clock_out_inner(jtag_info, core_regs[i], 0);
 	}
 	arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
-	
 }
 
 void arm7tdmi_load_word_regs(target_t *target, u32 mask)
@@ -549,7 +543,6 @@
 	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
 	arm7tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 1), NULL, 0);
-
 }
 
 void arm7tdmi_load_hword_reg(target_t *target, int num)
@@ -563,7 +556,6 @@
 	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
 	arm7tdmi_clock_out(jtag_info, ARMV4_5_LDRH_IP(num, 0), NULL, 0);
-
 }
 
 void arm7tdmi_load_byte_reg(target_t *target, int num)
@@ -577,7 +569,6 @@
 	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
 	arm7tdmi_clock_out(jtag_info, ARMV4_5_LDRB_IP(num, 0), NULL, 0);
-
 }
 
 void arm7tdmi_store_word_regs(target_t *target, u32 mask)
@@ -591,7 +582,6 @@
 	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
 	arm7tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask, 0, 1), NULL, 0);
-	
 }
 
 void arm7tdmi_store_hword_reg(target_t *target, int num)
@@ -605,7 +595,6 @@
 	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
 	arm7tdmi_clock_out(jtag_info, ARMV4_5_STRH_IP(num, 0), NULL, 0);
-
 }
 
 void arm7tdmi_store_byte_reg(target_t *target, int num)
@@ -619,7 +608,6 @@
 	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
 	arm7tdmi_clock_out(jtag_info, ARMV4_5_STRB_IP(num, 0), NULL, 0);
-
 }
 
 void arm7tdmi_write_pc(target_t *target, u32 pc)
@@ -658,7 +646,6 @@
 	
 	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
 	arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_B(0xfffffa, 0), 0);
-
 }
 
 void arm7tdmi_branch_resume_thumb(target_t *target)
@@ -720,7 +707,6 @@
 	
 	arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 1);
 	arm7tdmi_clock_out(jtag_info, ARMV4_5_T_B(0x7f8), NULL, 0);
-
 }
 		
 void arm7tdmi_build_reg_cache(target_t *target)
@@ -771,11 +757,9 @@
 
 int arm7tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
 {
-	
 	arm7tdmi_build_reg_cache(target);
 	
 	return ERROR_OK;
-	
 }
 
 int arm7tdmi_quit(void)
@@ -784,7 +768,7 @@
 	return ERROR_OK;
 }
 
-int arm7tdmi_init_arch_info(target_t *target, arm7tdmi_common_t *arm7tdmi, jtag_tap_t *tap, const char *variant)
+int arm7tdmi_init_arch_info(target_t *target, arm7tdmi_common_t *arm7tdmi, jtag_tap_t *tap)
 {
 	armv4_5_common_t *armv4_5;
 	arm7_9_common_t *arm7_9;
@@ -838,34 +822,22 @@
 	arm7tdmi->arch_info = NULL;
 	arm7tdmi->common_magic = ARM7TDMI_COMMON_MAGIC;
 	
-	if (variant)
-	{
-		arm7tdmi->variant = strdup(variant);
-	}
-	else
-	{
-		arm7tdmi->variant = strdup("");
-	}
-	
 	arm7_9_init_arch_info(target, arm7_9);
 
 	return ERROR_OK;
 }
 
-
-
 int arm7tdmi_target_create( struct target_s *target, Jim_Interp *interp )
 {
 	arm7tdmi_common_t *arm7tdmi;
 	
 	arm7tdmi = calloc(1,sizeof(arm7tdmi_common_t));
 	
-	arm7tdmi_init_arch_info(target, arm7tdmi, target->tap, target->variant);
+	arm7tdmi_init_arch_info(target, arm7tdmi, target->tap);
 	
 	return ERROR_OK;
 }
 
-
 int arm7tdmi_register_commands(struct command_context_s *cmd_ctx)
 {
 	int retval;
@@ -873,5 +845,4 @@
 	retval = arm7_9_register_commands(cmd_ctx);
 	
 	return retval;
-
 }
Index: src/target/arm7tdmi.h
===================================================================
--- src/target/arm7tdmi.h	(revision 1229)
+++ src/target/arm7tdmi.h	(working copy)
@@ -35,13 +35,12 @@
 typedef struct arm7tdmi_common_s
 {
 	int common_magic;
-	char *variant;
 	void *arch_info;
 	arm7_9_common_t arm7_9_common;
 } arm7tdmi_common_t;
 
 int arm7tdmi_register_commands(struct command_context_s *cmd_ctx);
-int arm7tdmi_init_arch_info(target_t *target, arm7tdmi_common_t *arm7tdmi, jtag_tap_t *tap, const char *variant);
+int arm7tdmi_init_arch_info(target_t *target, arm7tdmi_common_t *arm7tdmi, jtag_tap_t *tap);
 int arm7tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
 int arm7tdmi_examine(struct target_s *target);
 
Index: src/target/arm920t.c
===================================================================
--- src/target/arm920t.c	(revision 1229)
+++ src/target/arm920t.c	(working copy)
@@ -703,7 +703,6 @@
 	arm9tdmi_init_target(cmd_ctx, target);
 		
 	return ERROR_OK;
-	
 }
 
 int arm920t_quit(void)
@@ -712,14 +711,14 @@
 	return ERROR_OK;
 }
 
-int arm920t_init_arch_info(target_t *target, arm920t_common_t *arm920t, jtag_tap_t *tap, const char *variant)
+int arm920t_init_arch_info(target_t *target, arm920t_common_t *arm920t, jtag_tap_t *tap)
 {
 	arm9tdmi_common_t *arm9tdmi = &arm920t->arm9tdmi_common;
 	arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common;
 	
 	/* initialize arm9tdmi specific info (including arm7_9 and armv4_5)
 	 */
-	arm9tdmi_init_arch_info(target, arm9tdmi, tap, variant);
+	arm9tdmi_init_arch_info(target, arm9tdmi, tap);
 
 	arm9tdmi->arch_info = arm920t;
 	arm920t->common_magic = ARM920T_COMMON_MAGIC;
@@ -752,7 +751,7 @@
 {
 	arm920t_common_t *arm920t = calloc(1,sizeof(arm920t_common_t));
 	
-	arm920t_init_arch_info(target, arm920t, target->tap, target->variant);
+	arm920t_init_arch_info(target, arm920t, target->tap);
 
 	return ERROR_OK;
 }
Index: src/target/arm926ejs.c
===================================================================
--- src/target/arm926ejs.c	(revision 1229)
+++ src/target/arm926ejs.c	(working copy)
@@ -705,7 +705,6 @@
 	arm9tdmi_init_target(cmd_ctx, target);
 
 	return ERROR_OK;
-
 }
 
 int arm926ejs_quit(void)
@@ -714,14 +713,14 @@
 	return ERROR_OK;
 }
 
-int arm926ejs_init_arch_info(target_t *target, arm926ejs_common_t *arm926ejs, jtag_tap_t *tap, const char *variant)
+int arm926ejs_init_arch_info(target_t *target, arm926ejs_common_t *arm926ejs, jtag_tap_t *tap)
 {
 	arm9tdmi_common_t *arm9tdmi = &arm926ejs->arm9tdmi_common;
 	arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common;
 
 	/* initialize arm9tdmi specific info (including arm7_9 and armv4_5)
 	 */
-	arm9tdmi_init_arch_info(target, arm9tdmi, tap, variant);
+	arm9tdmi_init_arch_info(target, arm9tdmi, tap);
 
 	arm9tdmi->arch_info = arm926ejs;
 	arm926ejs->common_magic = ARM926EJS_COMMON_MAGIC;
@@ -755,7 +754,7 @@
 {
 	arm926ejs_common_t *arm926ejs = calloc(1,sizeof(arm926ejs_common_t));
 
-	arm926ejs_init_arch_info(target, arm926ejs, target->tap, target->variant);
+	arm926ejs_init_arch_info(target, arm926ejs, target->tap);
 
 	return ERROR_OK;
 }
Index: src/target/arm926ejs.h
===================================================================
--- src/target/arm926ejs.h	(revision 1229)
+++ src/target/arm926ejs.h	(working copy)
@@ -43,7 +43,7 @@
 	u32 d_far;
 } arm926ejs_common_t;
 
-extern int arm926ejs_init_arch_info(target_t *target, arm926ejs_common_t *arm926ejs, jtag_tap_t *tap, const char *variant);
+extern int arm926ejs_init_arch_info(target_t *target, arm926ejs_common_t *arm926ejs, jtag_tap_t *tap);
 extern int arm926ejs_register_commands(struct command_context_s *cmd_ctx); 
 extern int arm926ejs_arch_state(struct target_s *target); 
 extern int arm926ejs_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer); 
Index: src/target/arm966e.c
===================================================================
--- src/target/arm966e.c	(revision 1229)
+++ src/target/arm966e.c	(working copy)
@@ -102,12 +102,12 @@
 	return ERROR_OK;
 }
 
-int arm966e_init_arch_info(target_t *target, arm966e_common_t *arm966e, jtag_tap_t *tap, const char *variant)
+int arm966e_init_arch_info(target_t *target, arm966e_common_t *arm966e, jtag_tap_t *tap)
 {
 	arm9tdmi_common_t *arm9tdmi = &arm966e->arm9tdmi_common;
 	arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common;
 	
-	arm9tdmi_init_arch_info(target, arm9tdmi, tap, variant);
+	arm9tdmi_init_arch_info(target, arm9tdmi, tap);
 
 	arm9tdmi->arch_info = arm966e;
 	arm966e->common_magic = ARM966E_COMMON_MAGIC;
@@ -125,7 +125,7 @@
 {
 	arm966e_common_t *arm966e = calloc(1,sizeof(arm966e_common_t));
 	
-	arm966e_init_arch_info(target, arm966e, target->tap, target->variant);
+	arm966e_init_arch_info(target, arm966e, target->tap);
 
 	return ERROR_OK;
 }
Index: src/target/arm9tdmi.c
===================================================================
--- src/target/arm9tdmi.c	(revision 1229)
+++ src/target/arm9tdmi.c	(working copy)
@@ -507,7 +507,6 @@
 			/* nothing fetched, STM in MEMORY (i'th cycle) */
 			arm9tdmi_clock_data_in(jtag_info, core_regs[i]);
 	}
-
 }
 
 void arm9tdmi_read_core_regs_target_buffer(target_t *target, u32 mask, void* buffer, int size)
@@ -549,7 +548,6 @@
 					break;
 			}
 	}
-
 }
 
 void arm9tdmi_read_xpsr(target_t *target, u32 *xpsr, int spsr)
@@ -574,7 +572,6 @@
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 	/* nothing fetched, STR in MEMORY */
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, xpsr, 0);
-
 }
 
 void arm9tdmi_write_xpsr(target_t *target, u32 xpsr, int spsr)
@@ -664,7 +661,6 @@
 			arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, core_regs[i], NULL, 0);
 	}
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
-	
 }
 
 void arm9tdmi_load_word_regs(target_t *target, u32 mask)
@@ -677,7 +673,6 @@
 	/* put system-speed load-multiple into the pipeline */
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 1), 0, NULL, 0);
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
-
 }
 
 void arm9tdmi_load_hword_reg(target_t *target, int num)
@@ -702,7 +697,6 @@
 	/* put system-speed load byte into the pipeline */
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_LDRB_IP(num, 0), 0, NULL, 0);
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
-
 }
 
 void arm9tdmi_store_word_regs(target_t *target, u32 mask)
@@ -715,7 +709,6 @@
 	/* put system-speed store-multiple into the pipeline */
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask, 0, 1), 0, NULL, 0);
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
-
 }
 
 void arm9tdmi_store_hword_reg(target_t *target, int num)
@@ -728,7 +721,6 @@
 	/* put system-speed store half-word into the pipeline */
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_STRH_IP(num, 0), 0, NULL, 0);
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
-
 }
 
 void arm9tdmi_store_byte_reg(target_t *target, int num)
@@ -741,7 +733,6 @@
 	/* put system-speed store byte into the pipeline */
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_STRB_IP(num, 0), 0, NULL, 0);
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
-
 }
 
 void arm9tdmi_write_pc(target_t *target, u32 pc)
@@ -768,7 +759,6 @@
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 	/* fetch NOP, LDM in EXECUTE stage (5th cycle) */
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
-
 }
 
 void arm9tdmi_branch_resume(target_t *target)
@@ -780,7 +770,6 @@
 	
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_B(0xfffffc, 0), 0, NULL, 0);
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
-
 }
 
 void arm9tdmi_branch_resume_thumb(target_t *target)
@@ -841,7 +830,6 @@
 	
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_T_B(0x7f7), 0, NULL, 1);
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
-
 }
 
 void arm9tdmi_enable_single_step(target_t *target, u32 next_pc)
@@ -888,7 +876,6 @@
 	armv4_5->core_cache = (*cache_p);
 }
 
-
 int arm9tdmi_examine(struct target_s *target)
 {
 	/* get pointers to arch-specific information */
@@ -932,7 +919,6 @@
 	arm9tdmi_build_reg_cache(target);
 	
 	return ERROR_OK;
-	
 }
 
 int arm9tdmi_quit(void)
@@ -941,7 +927,7 @@
 	return ERROR_OK;
 }
 
-int arm9tdmi_init_arch_info(target_t *target, arm9tdmi_common_t *arm9tdmi, jtag_tap_t *tap, const char *variant)
+int arm9tdmi_init_arch_info(target_t *target, arm9tdmi_common_t *arm9tdmi, jtag_tap_t *tap)
 {
 	armv4_5_common_t *armv4_5;
 	arm7_9_common_t *arm7_9;
@@ -994,15 +980,6 @@
 	
 	arm9tdmi->common_magic = ARM9TDMI_COMMON_MAGIC;
 	arm9tdmi->arch_info = NULL;
-
-	if (variant)
-	{
-		arm9tdmi->variant = strdup(variant);
-	}
-	else
-	{
-		arm9tdmi->variant = strdup("");
-	}
 	
 	arm7_9_init_arch_info(target, arm7_9);
 
@@ -1045,13 +1022,11 @@
 	return ERROR_OK;
 }
 
-
-
 int arm9tdmi_target_create(struct target_s *target, Jim_Interp *interp)
 {
 	arm9tdmi_common_t *arm9tdmi = calloc(1,sizeof(arm9tdmi_common_t));
 
-	arm9tdmi_init_arch_info(target, arm9tdmi, target->tap, target->variant);
+	arm9tdmi_init_arch_info(target, arm9tdmi, target->tap);
 	
 	return ERROR_OK;
 }
@@ -1062,16 +1037,13 @@
 	
 	command_t *arm9tdmi_cmd;
 	
-		
 	retval = arm7_9_register_commands(cmd_ctx);
 	
 	arm9tdmi_cmd = register_command(cmd_ctx, NULL, "arm9tdmi", NULL, COMMAND_ANY, "arm9tdmi specific commands");
 
 	register_command(cmd_ctx, arm9tdmi_cmd, "vector_catch", handle_arm9tdmi_catch_vectors_command, COMMAND_EXEC, "catch arm920t vectors ['all'|'none'|'<vec1 vec2 ...>']");
 	
-	
 	return retval;
-
 }
 
 int handle_arm9tdmi_catch_vectors_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
Index: src/target/arm9tdmi.h
===================================================================
--- src/target/arm9tdmi.h	(revision 1229)
+++ src/target/arm9tdmi.h	(working copy)
@@ -35,7 +35,6 @@
 typedef struct arm9tdmi_common_s
 {
 	int common_magic;
-	char *variant;
 	void *arch_info;
 	arm7_9_common_t arm7_9_common;
 } arm9tdmi_common_t;
@@ -60,7 +59,7 @@
 
 extern int arm9tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
 int arm9tdmi_examine(struct target_s *target);
-extern int arm9tdmi_init_arch_info(target_t *target, arm9tdmi_common_t *arm9tdmi, jtag_tap_t *tap, const char *variant);
+extern int arm9tdmi_init_arch_info(target_t *target, arm9tdmi_common_t *arm9tdmi, jtag_tap_t *tap);
 extern int arm9tdmi_register_commands(struct command_context_s *cmd_ctx);
 
 extern int arm9tdmi_clock_out(arm_jtag_t *jtag_info, u32 instr, u32 out, u32 *in, int sysspeed);
Index: src/target/armv4_5.c
===================================================================
--- src/target/armv4_5.c	(revision 1229)
+++ src/target/armv4_5.c	(working copy)
@@ -178,7 +178,6 @@
 	"GDB dummy floating-point status register", armv4_5_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
 };
 
-
 int armv4_5_get_core_reg(reg_t *reg)
 {
 	int retval;
@@ -663,7 +662,6 @@
 	return retval;
 }
 
-
 int armv4_5_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info)
 {
 	return armv4_5_run_algorithm_inner(target, num_mem_params, mem_params, num_reg_params, reg_params, entry_point, exit_point, timeout_ms, arch_info, armv4_5_run_algorithm_completion);
Index: src/target/cortex_m3.c
===================================================================
--- src/target/cortex_m3.c	(revision 1229)
+++ src/target/cortex_m3.c	(working copy)
@@ -739,7 +739,7 @@
 	 * when srst is asserted the luminary device seesm to also clear the debug registers
 	 * which does not match the armv7 debug TRM */
 		
-	if (strcmp(cortex_m3->variant, "lm3s") == 0)
+	if (strcmp(target->variant, "lm3s") == 0)
 	{
 		/* get revision of lm3s target, only early silicon has this issue
 		 * Fury Rev B, DustDevil Rev B, Tempest all ok */
@@ -1510,7 +1510,7 @@
 	return ERROR_OK;
 }
 
-int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, jtag_tap_t *tap, const char *variant)
+int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, jtag_tap_t *tap)
 {
 	armv7m_common_t *armv7m;
 	armv7m = &cortex_m3->armv7m;
@@ -1538,15 +1538,6 @@
 	armv7m->pre_restore_context = NULL;
 	armv7m->post_restore_context = NULL;
 	
-	if (variant)
-	{
-		cortex_m3->variant = strdup(variant);
-	}
-	else
-	{
-		cortex_m3->variant = strdup("");
-	}
-	
 	armv7m_init_arch_info(target, armv7m);	
 	armv7m->arch_info = cortex_m3;
 	armv7m->load_core_reg_u32 = cortex_m3_load_core_reg_u32;
@@ -1561,7 +1552,7 @@
 {
 	cortex_m3_common_t *cortex_m3 = calloc(1,sizeof(cortex_m3_common_t));
 	
-	cortex_m3_init_arch_info(target, cortex_m3, target->tap, target->variant);
+	cortex_m3_init_arch_info(target, cortex_m3, target->tap);
 	
 	return ERROR_OK;
 }
Index: src/target/cortex_m3.h
===================================================================
--- src/target/cortex_m3.h	(revision 1229)
+++ src/target/cortex_m3.h	(working copy)
@@ -138,7 +138,6 @@
 {
 	int common_magic;
 	arm_jtag_t jtag_info;
-	char *variant;
 	
 	/* Context information */
 	u32 dcb_dhcsr;
@@ -189,6 +188,6 @@
 int cortex_m3_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
 
 extern int cortex_m3_register_commands(struct command_context_s *cmd_ctx);
-extern int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, jtag_tap_t *tap, const char *variant);
+extern int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, jtag_tap_t *tap);
 
 #endif /* CORTEX_M3_H */
Index: src/target/feroceon.c
===================================================================
--- src/target/feroceon.c	(revision 1229)
+++ src/target/feroceon.c	(working copy)
@@ -645,7 +645,7 @@
 	arm7_9_common_t *arm7_9;
 	arm926ejs_common_t *arm926ejs = calloc(1,sizeof(arm926ejs_common_t));
   
-	arm926ejs_init_arch_info(target, arm926ejs, target->tap, target->variant);
+	arm926ejs_init_arch_info(target, arm926ejs, target->tap);
 
 	armv4_5 = target->arch_info;
 	arm7_9 = armv4_5->arch_info;
Index: src/target/mips32.c
===================================================================
--- src/target/mips32.c	(revision 1229)
+++ src/target/mips32.c	(working copy)
@@ -320,7 +320,7 @@
 	return cache;
 }
 
-int mips32_init_arch_info(target_t *target, mips32_common_t *mips32, jtag_tap_t *tap, const char *variant)
+int mips32_init_arch_info(target_t *target, mips32_common_t *mips32, jtag_tap_t *tap)
 {
 	target->arch_info = mips32;
 	mips32->common_magic = MIPS32_COMMON_MAGIC;
Index: src/target/mips32.h
===================================================================
--- src/target/mips32.h	(revision 1229)
+++ src/target/mips32.h	(working copy)
@@ -119,7 +119,7 @@
 #define MIPS32_DRET					0x4200001F
 
 extern int mips32_arch_state(struct target_s *target);
-extern int mips32_init_arch_info(target_t *target, mips32_common_t *mips32, jtag_tap_t *tap, const char *variant);
+extern int mips32_init_arch_info(target_t *target, mips32_common_t *mips32, jtag_tap_t *tap);
 extern int mips32_restore_context(target_t *target);
 extern int mips32_save_context(target_t *target);
 extern reg_cache_t *mips32_build_reg_cache(target_t *target);
Index: src/target/mips_m4k.c
===================================================================
--- src/target/mips_m4k.c	(revision 1229)
+++ src/target/mips_m4k.c	(working copy)
@@ -265,7 +265,6 @@
 {
 	mips32_common_t *mips32 = target->arch_info;
 	mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
-	mips_m4k_common_t *mips_m4k = mips32->arch_info;
 	
 	LOG_DEBUG("target->state: %s", 
 		Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
@@ -288,7 +287,7 @@
 		mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT, NULL);
 	}
 	
-	if (strcmp(mips_m4k->variant, "ejtag_srst") == 0)
+	if (strcmp(target->variant, "ejtag_srst") == 0)
 	{
 		u32 ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_PRRST | EJTAG_CTRL_PERRST;
 		LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor...");
@@ -735,23 +734,14 @@
 	return ERROR_OK;
 }
 
-int mips_m4k_init_arch_info(target_t *target, mips_m4k_common_t *mips_m4k, jtag_tap_t *tap, const char *variant)
+int mips_m4k_init_arch_info(target_t *target, mips_m4k_common_t *mips_m4k, jtag_tap_t *tap)
 {
 	mips32_common_t *mips32 = &mips_m4k->mips32_common;
 	
-	if (variant)
-	{
-		mips_m4k->variant = strdup(variant);
-	}
-	else
-	{
-		mips_m4k->variant = strdup("");
-	}
-	
 	mips_m4k->common_magic = MIPSM4K_COMMON_MAGIC;
 	
 	/* initialize mips4k specific info */
-	mips32_init_arch_info(target, mips32, tap, variant);
+	mips32_init_arch_info(target, mips32, tap);
 	mips32->arch_info = mips_m4k;
 	
 	return ERROR_OK;
@@ -761,7 +751,7 @@
 {
 	mips_m4k_common_t *mips_m4k = calloc(1,sizeof(mips_m4k_common_t));
 	
-	mips_m4k_init_arch_info(target, mips_m4k, target->tap, target->variant);
+	mips_m4k_init_arch_info(target, mips_m4k, target->tap);
 	
 	return ERROR_OK;
 }
Index: src/target/mips_m4k.h
===================================================================
--- src/target/mips_m4k.h	(revision 1229)
+++ src/target/mips_m4k.h	(working copy)
@@ -32,8 +32,6 @@
 {
 	int common_magic;
 	mips32_common_t mips32_common;
-	
-	char *variant;
 } mips_m4k_common_t;
 
 extern int mips_m4k_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer);
Index: src/target/target.c
===================================================================
--- src/target/target.c	(revision 1229)
+++ src/target/target.c	(working copy)
@@ -3892,6 +3892,10 @@
 		target->endianness = TARGET_LITTLE_ENDIAN;
 	}
 
+	/* incase variant is not set */
+	if (!target->variant)
+		target->variant = strdup("");
+	
 	/* create the target specific commands */
 	if( target->type->register_commands ){
 		(*(target->type->register_commands))( cmd_ctx );
Index: src/target/target.h
===================================================================
--- src/target/target.h	(revision 1229)
+++ src/target/target.h	(working copy)
@@ -40,15 +40,15 @@
 struct reg_s;
 struct command_context_s;
 /*
-TARGET_UNKNOWN = 0: we don't know anything about the target yet
-TARGET_RUNNING = 1: the target is executing user code
-TARGET_HALTED  = 2: the target is not executing code, and ready to talk to the
-debugger. on an xscale it means that the debug handler is executing
-TARGET_RESET   = 3: the target is being held in reset (only a temporary state,
-not sure how this is used with all the recent changes)
-TARGET_DEBUG_RUNNING = 4: the target is running, but it is executing code on
-behalf of the debugger (e.g. algorithm for flashing)
-*/
+ * TARGET_UNKNOWN = 0: we don't know anything about the target yet
+ * TARGET_RUNNING = 1: the target is executing user code
+ * TARGET_HALTED  = 2: the target is not executing code, and ready to talk to the
+ * debugger. on an xscale it means that the debug handler is executing
+ * TARGET_RESET   = 3: the target is being held in reset (only a temporary state,
+ * not sure how this is used with all the recent changes)
+ * TARGET_DEBUG_RUNNING = 4: the target is running, but it is executing code on
+ * behalf of the debugger (e.g. algorithm for flashing) */
+
 enum target_state
 {
 	TARGET_UNKNOWN = 0,
@@ -228,7 +228,7 @@
 	 *
 	 * It is illegal to talk to the target at this stage as this fn is invoked
 	 * before the JTAG chain has been examined/verified
-     */
+	 * */
 	int (*init_target)(struct command_context_s *cmd_ctx, struct target_s *target);
 	int (*quit)(void);
 
@@ -237,21 +237,21 @@
 
 } target_type_t;
 
-// forward decloration
+/* forward decloration */
 typedef struct target_event_action_s target_event_action_t;
 
 typedef struct target_s
 {
 	target_type_t *type;				/* target type definition (name, access functions) */
-	const char *cmd_name;               /* tcl Name of target */
-	int target_number;                  /* generaly, target index but may not be in order */
-	jtag_tap_t *tap;                 /* where on the jtag chain is this */
-	const char *variant;                /* what varient of this chip is it? */
+	const char *cmd_name;				/* tcl Name of target */
+	int target_number;					/* generaly, target index but may not be in order */
+	jtag_tap_t *tap;					/* where on the jtag chain is this */
+	const char *variant;				/* what varient of this chip is it? */
 	target_event_action_t *event_action;
 
 	int reset_halt;						/* attempt resetting the CPU into the halted mode? */
 	u32 working_area;					/* working area (initialized RAM). Evaluated
-										   upon first allocation from virtual/physical address. */
+										 * upon first allocation from virtual/physical address. */
 	u32 working_area_virt;				/* virtual address */
 	u32 working_area_phys;				/* physical address */
 	u32 working_area_size;				/* size in bytes */
@@ -269,27 +269,27 @@
 	void *arch_info;					/* architecture specific information */
 	struct target_s *next;				/* next target in list */
 
-	int display; 						/* display async info in telnet session. Do not display
-										   lots of halted/resumed info when stepping in debugger. */
+	int display;						/* display async info in telnet session. Do not display
+										 * lots of halted/resumed info when stepping in debugger. */
 } target_t;
 
 enum target_event
 {
-	// OLD historical names
-	//  - Prior to the great TCL change
-	//  - June/July/Aug 2008
-	//  - Duane Ellis
+	/* LD historical names
+	 * - Prior to the great TCL change
+	 * - June/July/Aug 2008
+	 * - Duane Ellis */
 	TARGET_EVENT_OLD_gdb_program_config,
 	TARGET_EVENT_OLD_pre_reset,
 	TARGET_EVENT_OLD_post_reset,
 	TARGET_EVENT_OLD_pre_resume,
 
 	/* allow GDB to do stuff before others handle the halted event,
- 	this is in lieu of defining ordering of invocation of events,
- 	which would be more complicated */
- 	TARGET_EVENT_EARLY_HALTED,
- 	TARGET_EVENT_HALTED,		/* target entered debug state from normal execution or reset */
- 	TARGET_EVENT_RESUMED,		/* target resumed to normal execution */
+	 * this is in lieu of defining ordering of invocation of events,
+	 * which would be more complicated */
+	TARGET_EVENT_EARLY_HALTED,
+	TARGET_EVENT_HALTED,		/* target entered debug state from normal execution or reset */
+	TARGET_EVENT_RESUMED,		/* target resumed to normal execution */
 	TARGET_EVENT_RESUME_START,
 	TARGET_EVENT_RESUME_END,
 
@@ -308,14 +308,12 @@
 	TARGET_EVENT_RESET_INIT,
 	TARGET_EVENT_RESET_END,
 
+	TARGET_EVENT_DEBUG_HALTED,	/* target entered debug state, but was executing on behalf of the debugger */
+	TARGET_EVENT_DEBUG_RESUMED, /* target resumed to execute on behalf of the debugger */
 
- 	TARGET_EVENT_DEBUG_HALTED,	/* target entered debug state, but was executing on behalf of the debugger */
- 	TARGET_EVENT_DEBUG_RESUMED, /* target resumed to execute on behalf of the debugger */
-
 	TARGET_EVENT_EXAMINE_START,
 	TARGET_EVENT_EXAMINE_END,
 
-
 	TARGET_EVENT_GDB_ATTACH,
 	TARGET_EVENT_GDB_DETACH,
 
@@ -330,7 +328,7 @@
 struct target_event_action_s {
 	enum target_event event;
 	Jim_Obj *body;
-	int      has_percent;
+	int has_percent;
 	target_event_action_t *next;
  };
 
@@ -428,7 +426,6 @@
 void target_handle_event( target_t *t, enum target_event e);
 void target_all_handle_event( enum target_event e );
 
-
 #define ERROR_TARGET_INVALID	(-300)
 #define ERROR_TARGET_INIT_FAILED (-301)
 #define ERROR_TARGET_TIMEOUT	(-302)