Duane Ellis wrote:
Dirk/Rick,
I know the two of you have been messing with Beagle board more then I...
Dust has settled here and I'm in a position to start messing with it...
:)
Help from the experts is always welcome. Great!
While Rick already answered most of your questions, here my style of
the answers, maybe they help you, too:
Some questions:
1) Is there anything pending - SVN wise? or is that up to date?
SVN top is fine. I'm using 1285 from yesterday.
2) A copy of a recent config file you guys are using would be helpful.
Please find them in attachment. In omap3530.txt there are some
different options to try:
Regarding jtag newtap:
For jrc the -ircapture 0x1 -irmask 0xf one we started with. Then we
found that jrc ID code is at 0x4 and I switched to -ircapture 0x4
-irmask 0x0 as proposed by Rick. Maybe you like to review this.
Regarding cpu tap-enable:
There are three versions. The first one is the 'original' one which
circulated here at the mailing list, nobody can remember where it
comes from. I then compared this 'original' one with
http://elinux.org/BeagleBoardJTAG#BDI_config
and found to replace 0x81002148 at the third drscan with 0x81000081.
We don't know what these commands are doing, though.
Then looking at
http://elinux.org/OMAP3530_ICEPICK
what is from TI's document resulted in the third configuration. There,
I'm not sure about the "Embed the port address 0x0f000000 value 3" in
TI's documentation.
3) A short summary - of the *LONG* chain of emails would be helpful.
Where are you, what is known, unknown, etc.
Independent of which of the above configurations you use, the status
is always the same for me (see log below, too):
* starting OpenOCD, doing a
irscan omap3530.jrc 4
drscan omap3530.jrc 32 0x0
returns jrc IdCode.
* Doing then a
jtag tapenable omap3530.cpu
and afterwards jrc IdCode isn't acessible any more with above commands.
* Doing a hack in OpenOCD in jtag.c in JTAG_CMD_TAPENABLE by disabling
"t->enabled":
case JTAG_CMD_TAPENABLE:
jtag_tap_handle_event( t, JTAG_TAP_EVENT_ENABLE);
e = 1;
//t->enabled = e; // <====== !!
break;
results in jrc IdCode readable even after tapenable (not in the log
below, see mail history from yesterday).
* In TI doc
http://elinux.org/OMAP3530_ICEPICK
there is a
## Function : Wait for a minimum number of TCLK pulses.
Parameter : The count of TCLK pulses is '10'.
At the moment we 'emulate' this by runtest 10. As I understand it, we
are not sure if this correct as it touches state machine while it
isn't ready yet. What I understand we might need a new OpenOCD
function "wait 10 TCKs without touching anything".
* Once we have omap3530.cpu working correctly, we assume IdCode at IR
0xE. So we assume
irscan omap3530.cpu 0xe
drscan omap3530.cpu 32 0x0
returning a Coresight ID should be the final goal to prove that we can
access it.
* At the moment we discuss to get an better idea how the scan chain
might be configured after tapenable (didn't read last mail from Rick
yet). This is the discussion with 0x55aa55aa.
That's it for the moment.
Best regards
Dirk
-- cut --
> scan_chain
TapName | Enabled | IdCode Expected IrLen
IrCap IrMask Instr
---|--------------------|---------|------------|------------|------|------|------|--------
-
0 | omap3530.jrc | Y | 0x0b7ae02f | 0x0b7ae02f | 0x06 |
0x04 | 0x00 | 0x3f
1 | omap3530.cpu | n | 0x00000000 | 0xffffffff | 0x04 |
0x01 | 0x00 | 0x0f
> irscan omap3530.jrc 0
> drscan omap3530.jrc 32 0x0
00000000
> irscan omap3530.jrc 4
> drscan omap3530.jrc 32 0x0
0b7ae02f
> irscan omap3530.jrc 4
> drscan omap3530.jrc 32 0x55aa55aa
0b7ae02f
> jtag tapenable omap3530.cpu
Enabling Cortex-A8 @ OMAP3
Cortex-A8 @ OMAP3 enabled
1
> irscan omap3530.jrc 4
> drscan omap3530.jrc 32 0x0
00000000
> irscan omap3530.jrc 4
> drscan omap3530.jrc 32 0x55aa55aa
00000000
-- cut --
#TI OMAP3530 processor - http://www.ti.com
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME omap3530
}
if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
} else {
# this defaults to a little endianness
set _ENDIAN little
}
if { [info exists CPUTAPID ] } {
set _CPUTAPID $CPUTAPID
} else {
# force an error till we get a good number
set _CPUTAPID 0xffffffff
}
#jtag scan chain
#jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0xf -expected-id
0x0b7ae02f
jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x4 -irmask 0x0 -expected-id
0x0b7ae02f
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0 -expected-id
$_CPUTAPID -disable
#jtag configure $_CHIPNAME.cpu -event tap-enable {
# puts "Enabling Cortex-A8 @ OMAP3"
# irscan omap3530.jrc 7
# drscan omap3530.jrc 8 0x89
# irscan omap3530.jrc 2
# drscan omap3530.jrc 32 0x81000080
# drscan omap3530.jrc 32 0xa3002048
# drscan omap3530.jrc 32 0x81000081
# drscan omap3530.jrc 32 0xa3002148
# runtest 10
# puts "Cortex-A8 @ OMAP3 enabled"
#}
#jtag configure $_CHIPNAME.cpu -event tap-enable {
# puts "Enabling Cortex-A8 @ OMAP3"
# irscan omap3530.jrc 7
# drscan omap3530.jrc 8 0x89
# irscan omap3530.jrc 2
# drscan omap3530.jrc 32 0x81000080
# drscan omap3530.jrc 32 0xa3002048
# drscan omap3530.jrc 32 0x81002148
# drscan omap3530.jrc 32 0xa3002148
# runtest 10
# puts "Cortex-A8 @ OMAP3 enabled"
#}
jtag configure $_CHIPNAME.cpu -event tap-enable {
puts "Enabling Cortex-A8 @ OMAP3"
irscan omap3530.jrc 7
drscan omap3530.jrc 8 0x89
irscan omap3530.jrc 2
# Embed the port address 0x0f000000 value 3 ?
drscan omap3530.jrc 32 0xa3002108
runtest 10
puts "Cortex-A8 @ OMAP3 enabled"
}
#Basic configuration
telnet_port 4444
gdb_port 3333
#Interface
source [find interface/flyswatter.cfg]
#jtag scan chain
source [find target/omap3530.cfg]
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