Peter Denison wrote: > The symptoms are that the adapter will initialise OK, but toward the end > of a 'reset halt', after the 2030 TCK cycles, and after loading the Mini > I-cache, the DCSR write is OK, but the first capture from the TX register > fails. >
peter> This can only be in the adapter-specific code, No - it could also be something specific about how the adapter interprets commands that where not known or a non-issue to other targets. Hmm - how do you know 2030 clocks? Do you have some type of a timing thing hooked up and watching the pins wiggle? If so it would be interesting to compare the two traces some how. -Duane. _______________________________________________ Openocd-development mailing list [email protected] https://lists.berlios.de/mailman/listinfo/openocd-development
