> To: [email protected]
> Subject: Re: [Openocd-development] Cortex M3 halting almost
> immediately
>
> I've narrowed it down (I think) to a multiple bugs in
> cortex_m3.c. Can somebody who knows the codebase a little
> better take a look and verify if it's an actual bug? Here's
> what I think is going on.
>
> bug 1) cortex_m3_assert_reset() called
> cortex_m3_clear_halt(), which contrary to its name, doesn't
> clear the halt flag, but instead sets C_HALT.
>
> bug 2) cortex_m3_poll() does an atomic read on DCB_DHCSR,
> checks if the target is resetting, and then calls
> cortex_m3_endreset_event(), which should reset the DHCSR to
> its reset state. Unfortunately, the atomic read which checks
> that state is called before endreset_event(), so when it
> checks (dcb_dhcsr & S_HALT), it's using the old value of
> DHCSR, then halts the target, leaving you right back where
> you started (halted).
>
> Making assert_reset() actually clear C_HALT and adding another read in
> poll() fixed the problem for me.
>
Sure was a bug - i have committed a slightly tweaked version of your patch.
Mainly so we preserve any interrupt masking that is enabled.
Index: cortex_m3.c
===================================================================
--- cortex_m3.c (revision 1412)
+++ cortex_m3.c (revision 1413) @@ -243,6 +243,10 @@
swjdp_transaction_endcheck(swjdp);
armv7m_invalidate_core_regs(target);
+
+ /* make sure we have latest dhcsr flags */
+ ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR,
&cortex_m3->dcb_dhcsr);
+
return ERROR_OK;
}
@@ -724,8 +728,12 @@
/* Set/Clear C_MASKINTS in a separate operation */
if (cortex_m3->dcb_dhcsr & C_MASKINTS)
ahbap_write_system_atomic_u32(swjdp, DCB_DHCSR,
DBGKEY | C_DEBUGEN | C_HALT);
-
+
+ /* clear any debug flags before resuming */
cortex_m3_clear_halt(target);
+
+ /* clear C_HALT in dhcsr reg */
+ cortex_m3_write_debug_halt_mask(target, 0, C_HALT);
/* Enter debug state on reset, cf. end_reset_event() */
ahbap_write_system_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR
| VC_BUSERR);
Cheers
Spen
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