Hi, i'm currently writing a new target driver for supporting the Lattice Mico32 Soft CPU running on Lattice FGPAs. Well.. actually the soc-lm32 variant running on the Spartan-3E Starterkit (its a 'port' to Xilinx FPGAs). It is a promising open soft cpu with upcoming support in vanilla newlib/binutils/gcc and gdb.
I (almost) completed a jtag driver for the Xilinx Platform Cable. Unfortunately the cable neither support TRST nor SRST. So my first question is, what to do with the 'reset' commands? Should they be implemented (in the jtag and/or target driver), although i don't have that functionality? At the moment, a 'reset [run|halt]' will trigger a 'bug: unknown jtag command type encountered'. (i have 'reset_config none' in my openocd.cfg) The only thing i can do is a soft reset. There is a special reset command, that can be sent over jtag, which reset the target cpu (actually it sets the PC to its default value). The debugging works with the help of a monitor program. When an exception or breakpoint/watchpoint occurs, it dumps the registers and waits for instructions. The monitor sends and receives messages over a simple JTAG UART. An emulated 'reset halt' would be remapping the reset vector to the monitor program and soft reset the cpu. For a 'reset run' i would just soft reset the cpu. Current status: + xpc jtag driver completed + monitor code completed + lm32 target + memory read/write complete + basic halt and resume support The second question so far, is there any documentation about the reg_cache* types and functions? PS. if someone is interested there is a reference manual at http://www.latticesemi.com/dynamic/view_document.cfm?document_id=20890 -- Best regards, Michael --- Don't cry because it is over, smile because it happened. _______________________________________________ Openocd-development mailing list [email protected] https://lists.berlios.de/mailman/listinfo/openocd-development
