I am using an evaluator 7T board with an Olimex olimex-arm-usb-ocd JTAG interface.
With Open On-Chip Debugger 1.0 (2009-02-17-17:36) svn:1374 I have tested this two files for this board. If somebody want to check and include in next releases ... + modified arm_evaluator7t.cfg : # I add this reset specification : ******************************************************************* reset_config trst_and_srst separate trst_open_drain srst_open_drain ******************************************************************* + _eval7t.startup (set of gdb commands in order to set the same memory mapping used by BSL and Angel (with RAM at adress 0) ******************************************************************* # SYSCONFIG : SDRAM Special regs 3FF0000 SRAM 8k 3FE0000 no cache/wbuf mo mww 0x03ff0000 0x07ffffa0 # CKLCON : no clock divide no mux no wait mo mww 0x03ff3000 0x00000000 # Bank0 : 16 bits banks 1 and 2 : 32 bits no DRAM mo mww 0x03ff3010 0x0000003e # ROMCON0 16 bits ROM [1800000,1880000[ tacc=4 pmc = normal mo mww 0x03ff3014 0x18860030 # ROMCON1 used by SRAM [00000,40000[ tacc=2 pmc = normal mo mww 0x03ff3018 0x00400010 # ROMCOM2 used by SRAM [04000,80000[ tacc=2 pmc = normal mo mww 0x03ff301c 0x00801010 # ROMCON3 not used [600000, 800000[ mo mww 0x03ff3020 0x08018020 # ROMCON4 not used [100000,20000[ mo mww 0x03ff3024 0x0a020040 # ROMCON5 not used [A00000,c00000[ mo mww 0x03ff3028 0x0c028040 # REFEXTCON not used extern IO [360000,3610000[ refesh 4e1 tcsr=0 tchr=0 Ren=1 Vsf=1 mo mww 0x03ff303c 0x9c218360 ******************************************************************* Ph. W. -- ----------------------------------------------------------------------------- Philippe WAILLE email : [email protected] IMAG ID (Informatique et distribution) Tel : 04 76 61 20 13 ENSIMAG - antenne de Montbonnot Foreign : 33 4 76 61 20 13 INOVALLEE Fax : 04 76 61 20 99 51, avenue Jean Kuntzmann 38330 MONTBONNOT SAINT MARTIN
# This board is from ARM and has an samsung s3c45101x01 chip source [find target/samsung_s3c4510.cfg] # # FIXME: # Add (A) sdram configuration # Add (B) flash cfi programing configuration # # Modified by Philippe Waille 10 March 2009 # Eval7t has separate open drain reset signals reset_config trst_and_srst separate trst_open_drain srst_open_drain
# mo reset halt # # SYSCONFIG : SDRAM Special regs 3FF0000 SRAM 8k 3FE0000 no cache/wbuf mo mww 0x03ff0000 0x07ffffa0 # CKLCON : no clock divide no mux no wait mo mww 0x03ff3000 0x00000000 # Bank0 : 16 bits banks 1 and 2 : 32 bits no DRAM mo mww 0x03ff3010 0x0000003e # ROMCON0 16 bits ROM [1800000,1880000[ tacc=4 pmc = normal mo mww 0x03ff3014 0x18860030 # ROMCON1 used by SRAM [00000,40000[ tacc=2 pmc = normal mo mww 0x03ff3018 0x00400010 # ROMCOM2 used by SRAM [04000,80000[ tacc=2 pmc = normal mo mww 0x03ff301c 0x00801010 # ROMCON3 not used [600000, 800000[ mo mww 0x03ff3020 0x08018020 # ROMCON4 not used [100000,20000[ mo mww 0x03ff3024 0x0a020040 # ROMCON5 not used [A00000,c00000[ mo mww 0x03ff3028 0x0c028040 # REFEXTCON not used extern IO [360000,3610000[ refesh 4e1 tcsr=0 tchr=0 Ren=1 Vsf=1 mo mww 0x03ff303c 0x9c218360 # # RS232 CONFIG # ULCON 0/1 : no IRmode, MCLK, No parity, 1 stop bits, 8 bits mo mww 0x03ffD000 0x03 mo mww 0x03ffE000 0x03 # UCON 0/1 : /loop /break DSR TX_itreq RX_status_it RX_itreq mo mww 0x03ffD004 0x29 mo mww 0x03ffE004 0x29 # UBRDIV 0/1 : baud rate divisor # MCLOCK = 50 Mhz, MCLOCK2=25 MHz CNT1 = 0 CNT0=12 (115K) # baud/CNT0 : 230,4K/6 460,86K/2 # baud/CNT0 : 115,2K/13 57,6K/26 38,4K/40 19,2K/80 9,6K/162 4,8K/324 mo mww 0x03ffd014 0xc0 mo mww 0x03ffe014 0xc0
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