Zach Welch wrote: > On Wed, 2009-04-22 at 11:07 -0700, Rick Altherr wrote: > [snip] > >> This is an interesting idea, but I think it skips an important step. >> There seem to be a number of problems solely within the JTAG and >> interface layers. It would be great if someone constructed some >> infrastructure for a regression suite that looked at just those >> layers. That way we could verify those layers are functioning >> properly across the board and do so in a way where people with the >> correct equipment could quickly run the test periodically. >> > > I don't know why I forgot it myself, but a test suite is now on The List > with numerous bullets beneath it. >
Yes, this is an FPGA with a serial port on it? The is your universal JTAG TAP emulator, which gives feedback about the path than an actual TAP is traversing. Without a device to connect to, one that gives responses back, how do you verify success? _______________________________________________ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development
